From 0a1f56fb901534a4c250fb6b932e4f1d963bba82 Mon Sep 17 00:00:00 2001
From: Rob Clark <rob.clark@oss.qualcomm.com>
Date: Tue, 16 Sep 2025 07:38:40 -0700
Subject: [PATCH] freedreno/devices: Update chicken bits

b22 should be set on all a7xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37411>
---
 src/freedreno/common/freedreno_devices.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index 8b911c290b8..a467ca9ee35 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -995,7 +995,7 @@ a730_raw_magic_regs = [
         [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004],
         [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
 
-        [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00002400],
+        [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00402400],
         [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
         [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
@@ -1050,7 +1050,7 @@ a740_raw_magic_regs = [
         [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
         [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
 
-        [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
+        [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400],
         [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800],
         [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
         [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
@@ -1151,7 +1151,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
             [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
 
-            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
+            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
             [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
@@ -1223,7 +1223,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
             [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000700],
 
-            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
+            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430820],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
             [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
@@ -1322,7 +1322,7 @@ add_gpus([
             [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
             [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
             [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080],
-            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400000],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00431800],
             [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00800000],
             [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000],