From 094e20f13491d94b0cc457728a7c54cce87825b4 Mon Sep 17 00:00:00 2001
From: David Rosca <david.rosca@amd.com>
Date: Wed, 5 Nov 2025 14:39:58 +0100
Subject: [PATCH] radeonsi/vcn: Use radeon_bitstream functions to code headers

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38260>
---
 .../drivers/radeonsi/radeon_vcn_enc_1_2.c     | 404 +++---------------
 .../drivers/radeonsi/radeon_vcn_enc_4_0.c     | 197 +--------
 2 files changed, 54 insertions(+), 547 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
index 3fddb64a5cb..4e87e2d9107 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_1_2.c
@@ -180,390 +180,65 @@ static void radeon_enc_quality_params(struct radeon_encoder *enc)
 unsigned int radeon_enc_write_sps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
 {
    struct radeon_bitstream bs;
-   struct radeon_enc_pic *pic = &enc->enc_pic;
-   struct pipe_h264_enc_seq_param *sps = &pic->h264.desc->seq;
-
    radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_set_emulation_prevention(&bs, false);
-   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
-   radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
-   radeon_bs_set_emulation_prevention(&bs, true);
-   radeon_bs_code_fixed_bits(&bs, pic->spec_misc.profile_idc, 8);
-   radeon_bs_code_fixed_bits(&bs, sps->enc_constraint_set_flags, 6);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* reserved_zero_2bits */
-   radeon_bs_code_fixed_bits(&bs, pic->spec_misc.level_idc, 8);
-   radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
-
-   if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
-       pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
-       pic->spec_misc.profile_idc == 44  || pic->spec_misc.profile_idc == 83 ||
-       pic->spec_misc.profile_idc == 86  || pic->spec_misc.profile_idc == 118 ||
-       pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
-      radeon_bs_code_ue(&bs, 0x1); /* chroma_format_idc */
-      radeon_bs_code_ue(&bs, 0x0); /* bit_depth_luma_minus8 */
-      radeon_bs_code_ue(&bs, 0x0); /* bit_depth_chroma_minus8 */
-      radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* qpprime_y_zero_transform_bypass_flag + seq_scaling_matrix_present_flag */
-   }
-
-   radeon_bs_code_ue(&bs, sps->log2_max_frame_num_minus4);
-   radeon_bs_code_ue(&bs, sps->pic_order_cnt_type);
-
-   if (sps->pic_order_cnt_type == 0) {
-      radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
-   } else if (sps->pic_order_cnt_type == 1) {
-      radeon_bs_code_fixed_bits(&bs, sps->delta_pic_order_always_zero_flag, 1);
-      radeon_bs_code_se(&bs, sps->offset_for_non_ref_pic);
-      radeon_bs_code_se(&bs, sps->offset_for_top_to_bottom_field);
-      radeon_bs_code_ue(&bs, sps->num_ref_frames_in_pic_order_cnt_cycle);
-      for (unsigned i = 0; i < sps->num_ref_frames_in_pic_order_cnt_cycle; i++)
-         radeon_bs_code_se(&bs, sps->offset_for_ref_frame[i]);
-   }
-
-   radeon_bs_code_ue(&bs, sps->max_num_ref_frames);
-   radeon_bs_code_fixed_bits(&bs, sps->gaps_in_frame_num_value_allowed_flag, 1);
-   radeon_bs_code_ue(&bs, (pic->session_init.aligned_picture_width / 16 - 1));
-   radeon_bs_code_ue(&bs, (pic->session_init.aligned_picture_height / 16 - 1));
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* frame_mbs_only_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* direct_8x8_inference_flag */
-
-   radeon_bs_code_fixed_bits(&bs, sps->enc_frame_cropping_flag, 1);
-   if (sps->enc_frame_cropping_flag) {
-      radeon_bs_code_ue(&bs, sps->enc_frame_crop_left_offset);
-      radeon_bs_code_ue(&bs, sps->enc_frame_crop_right_offset);
-      radeon_bs_code_ue(&bs, sps->enc_frame_crop_top_offset);
-      radeon_bs_code_ue(&bs, sps->enc_frame_crop_bottom_offset);
-   }
-
-   radeon_bs_code_fixed_bits(&bs, sps->vui_parameters_present_flag, 1);
-   if (sps->vui_parameters_present_flag) {
-      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
-      if (sps->vui_flags.aspect_ratio_info_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
-         if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
-            radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
-            radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
-         }
-      }
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
-      if (sps->vui_flags.overscan_info_present_flag)
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
-      if (sps->vui_flags.video_signal_type_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
-         radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
-         if (sps->vui_flags.colour_description_present_flag) {
-            radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
-            radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
-            radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
-         }
-      }
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
-      if (sps->vui_flags.chroma_loc_info_present_flag) {
-         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
-         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
-      }
-      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
-      if (sps->vui_flags.timing_info_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
-         radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
-         radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.fixed_frame_rate_flag), 1);
-      }
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.nal_hrd_parameters_present_flag, 1);
-      if (sps->vui_flags.nal_hrd_parameters_present_flag)
-         radeon_bs_h264_hrd_parameters(&bs, &sps->nal_hrd_parameters);
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.vcl_hrd_parameters_present_flag, 1);
-      if (sps->vui_flags.vcl_hrd_parameters_present_flag)
-         radeon_bs_h264_hrd_parameters(&bs, &sps->vcl_hrd_parameters);
-      if (sps->vui_flags.nal_hrd_parameters_present_flag || sps->vui_flags.vcl_hrd_parameters_present_flag)
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.low_delay_hrd_flag, 1);
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.pic_struct_present_flag, 1);
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.bitstream_restriction_flag, 1);
-      if (sps->vui_flags.bitstream_restriction_flag) {
-         radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
-         radeon_bs_code_ue(&bs, 0x0); /* max_bytes_per_pic_denom */
-         radeon_bs_code_ue(&bs, 0x0); /* max_bits_per_mb_denom */
-         radeon_bs_code_ue(&bs, 16); /* log2_max_mv_length_horizontal */
-         radeon_bs_code_ue(&bs, 16); /* log2_max_mv_length_vertical */
-         radeon_bs_code_ue(&bs, sps->max_num_reorder_frames);
-         radeon_bs_code_ue(&bs, sps->max_dec_frame_buffering);
-      }
-   }
-
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
-   radeon_bs_byte_align(&bs);
-
+   radeon_bs_h264_sps(&bs, nal_byte, &enc->enc_pic.h264.desc->seq);
    return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_sps_hevc(struct radeon_encoder *enc, uint8_t *out)
 {
-   struct radeon_bitstream bs;
-   struct radeon_enc_pic *pic = &enc->enc_pic;
-   struct pipe_h265_enc_seq_param *sps = &pic->hevc.desc->seq;
-   int i;
-
-   radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_set_emulation_prevention(&bs, false);
-   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
-   radeon_bs_code_fixed_bits(&bs, 0x4201, 16);
-   radeon_bs_set_emulation_prevention(&bs, true);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* sps_video_parameter_set_id */
-   radeon_bs_code_fixed_bits(&bs, sps->sps_max_sub_layers_minus1, 3);
-   radeon_bs_code_fixed_bits(&bs, sps->sps_temporal_id_nesting_flag, 1);
-   radeon_bs_hevc_profile_tier_level(&bs, sps->sps_max_sub_layers_minus1, &sps->profile_tier_level);
-   radeon_bs_code_ue(&bs, 0x0); /* sps_seq_parameter_set_id */
-   radeon_bs_code_ue(&bs, sps->chroma_format_idc);
-   radeon_bs_code_ue(&bs, pic->session_init.aligned_picture_width);
-   radeon_bs_code_ue(&bs, pic->session_init.aligned_picture_height);
-
-   radeon_bs_code_fixed_bits(&bs, sps->conformance_window_flag, 1);
-   if (sps->conformance_window_flag) {
-      radeon_bs_code_ue(&bs, sps->conf_win_left_offset);
-      radeon_bs_code_ue(&bs, sps->conf_win_right_offset);
-      radeon_bs_code_ue(&bs, sps->conf_win_top_offset);
-      radeon_bs_code_ue(&bs, sps->conf_win_bottom_offset);
-   }
-
-   radeon_bs_code_ue(&bs, sps->bit_depth_luma_minus8);
-   radeon_bs_code_ue(&bs, sps->bit_depth_chroma_minus8);
-   radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
-   radeon_bs_code_fixed_bits(&bs, sps->sps_sub_layer_ordering_info_present_flag, 1);
-   i = sps->sps_sub_layer_ordering_info_present_flag ? 0 : sps->sps_max_sub_layers_minus1;
-   for (; i <= sps->sps_max_sub_layers_minus1; i++) {
-      radeon_bs_code_ue(&bs, sps->sps_max_dec_pic_buffering_minus1[i]);
-      radeon_bs_code_ue(&bs, sps->sps_max_num_reorder_pics[i]);
-      radeon_bs_code_ue(&bs, sps->sps_max_latency_increase_plus1[i]);
-   }
-
-   unsigned log2_diff_max_min_luma_coding_block_size =
-      6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3);
-   unsigned log2_min_transform_block_size_minus2 =
+   struct pipe_h265_enc_seq_param sps = enc->enc_pic.hevc.desc->seq;
+   sps.pic_width_in_luma_samples = enc->enc_pic.session_init.aligned_picture_width;
+   sps.pic_height_in_luma_samples = enc->enc_pic.session_init.aligned_picture_height;
+   sps.log2_min_luma_coding_block_size_minus3 =
       enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3;
-   unsigned log2_diff_max_min_transform_block_size = log2_diff_max_min_luma_coding_block_size;
-   unsigned max_transform_hierarchy_depth_inter = log2_diff_max_min_luma_coding_block_size + 1;
-   unsigned max_transform_hierarchy_depth_intra = max_transform_hierarchy_depth_inter;
-
-   radeon_bs_code_ue(&bs, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
-   radeon_bs_code_ue(&bs, log2_diff_max_min_luma_coding_block_size);
-   radeon_bs_code_ue(&bs, log2_min_transform_block_size_minus2);
-   radeon_bs_code_ue(&bs, log2_diff_max_min_transform_block_size);
-   radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_inter);
-   radeon_bs_code_ue(&bs, max_transform_hierarchy_depth_intra);
-
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* scaling_list_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, !pic->hevc_spec_misc.amp_disabled, 1);
-   radeon_bs_code_fixed_bits(&bs, !pic->hevc_deblock.disable_sao, 1);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pcm_enabled_flag */
-
-   radeon_bs_code_ue(&bs, sps->num_short_term_ref_pic_sets);
-   for (i = 0; i < sps->num_short_term_ref_pic_sets; i++)
-      radeon_bs_hevc_st_ref_pic_set(&bs, i, sps->num_short_term_ref_pic_sets, sps->st_ref_pic_set);
-
-   radeon_bs_code_fixed_bits(&bs, sps->long_term_ref_pics_present_flag, 1);
-   if (sps->long_term_ref_pics_present_flag) {
-      radeon_bs_code_ue(&bs, sps->num_long_term_ref_pics_sps);
-      for (i = 0; i < sps->num_long_term_ref_pics_sps; i++) {
-         radeon_bs_code_fixed_bits(&bs, sps->lt_ref_pic_poc_lsb_sps[i], sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
-         radeon_bs_code_fixed_bits(&bs, sps->used_by_curr_pic_lt_sps_flag[i], 1);
-      }
-   }
-
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sps_temporal_mvp_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
-
-   /* VUI parameters present flag */
-   radeon_bs_code_fixed_bits(&bs, (sps->vui_parameters_present_flag), 1);
-   if (sps->vui_parameters_present_flag) {
-      /* aspect ratio present flag */
-      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
-      if (sps->vui_flags.aspect_ratio_info_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
-         if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
-            radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
-            radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
-         }
-      }
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
-      if (sps->vui_flags.overscan_info_present_flag)
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
-      /* video signal type present flag  */
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
-      if (sps->vui_flags.video_signal_type_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
-         radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
-         if (sps->vui_flags.colour_description_present_flag) {
-            radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
-            radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
-            radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
-         }
-      }
-      /* chroma loc info present flag */
-      radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
-      if (sps->vui_flags.chroma_loc_info_present_flag) {
-         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
-         radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
-      }
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* neutral chroma indication flag */
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* field seq flag */
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* frame field info present flag */
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* default display windows flag */
-      /* vui timing info present flag */
-      radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
-      if (sps->vui_flags.timing_info_present_flag) {
-         radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
-         radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.poc_proportional_to_timing_flag, 1);
-         if (sps->vui_flags.poc_proportional_to_timing_flag)
-            radeon_bs_code_ue(&bs, sps->num_ticks_poc_diff_one_minus1);
-         radeon_bs_code_fixed_bits(&bs, sps->vui_flags.hrd_parameters_present_flag, 1);
-         if (sps->vui_flags.hrd_parameters_present_flag)
-            radeon_bs_hevc_hrd_parameters(&bs, 1, sps->sps_max_sub_layers_minus1, &sps->hrd_parameters);
-      }
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* bitstream restriction flag */
-   }
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1);  /* sps extension present flag */
-
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
-   radeon_bs_byte_align(&bs);
+   sps.log2_diff_max_min_luma_coding_block_size = 6 - (sps.log2_min_luma_coding_block_size_minus3 + 3);
+   sps.log2_min_transform_block_size_minus2 = sps.log2_min_luma_coding_block_size_minus3;
+   sps.log2_diff_max_min_transform_block_size = sps.log2_diff_max_min_luma_coding_block_size;
+   sps.max_transform_hierarchy_depth_inter = sps.log2_diff_max_min_luma_coding_block_size + 1;
+   sps.max_transform_hierarchy_depth_intra = sps.max_transform_hierarchy_depth_inter;
+   sps.sample_adaptive_offset_enabled_flag = !enc->enc_pic.hevc_deblock.disable_sao;
 
+   struct radeon_bitstream bs;
+   radeon_bs_reset(&bs, out, NULL);
+   radeon_bs_hevc_sps(&bs, &sps);
    return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_pps(struct radeon_encoder *enc, uint8_t nal_byte, uint8_t *out)
 {
+   struct pipe_h264_enc_pic_control pps = enc->enc_pic.h264.desc->pic_ctrl;
+   pps.weighted_bipred_idc = enc->enc_pic.spec_misc.weighted_bipred_idc;
+   pps.transform_8x8_mode_flag = enc->enc_pic.spec_misc.transform_8x8_mode;
+
    struct radeon_bitstream bs;
-
    radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_set_emulation_prevention(&bs, false);
-   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
-   radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
-   radeon_bs_set_emulation_prevention(&bs, true);
-   radeon_bs_code_ue(&bs, 0x0); /* pic_parameter_set_id */
-   radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
-   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
-   radeon_bs_code_ue(&bs, 0x0); /* num_slice_groups_minus_1 */
-   radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l0_default_active_minus1);
-   radeon_bs_code_ue(&bs, enc->enc_pic.h264.desc->pic_ctrl.num_ref_idx_l1_default_active_minus1);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* weighted_pred_flag */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.spec_misc.weighted_bipred_idc, 2);
-   radeon_bs_code_se(&bs, 0x0); /* pic_init_qp_minus26 */
-   radeon_bs_code_se(&bs, 0x0); /* pic_init_qs_minus26 */
-   radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
-   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
-   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.constrained_intra_pred_flag), 1);
-   radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
-   if (enc->enc_pic.h264.desc->pic_ctrl.more_rbsp_data) {
-      radeon_bs_code_fixed_bits(&bs, (enc->enc_pic.spec_misc.transform_8x8_mode), 1);
-      radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pic_scaling_matrix_present_flag */
-      radeon_bs_code_se(&bs, enc->enc_pic.h264_deblock.cr_qp_offset); /* second_chroma_qp_index_offset */
-   }
-
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
-   radeon_bs_byte_align(&bs);
-
+   radeon_bs_h264_pps(&bs, nal_byte, &pps);
    return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_pps_hevc(struct radeon_encoder *enc, uint8_t *out)
 {
+   struct pipe_h265_enc_pic_param pps = enc->enc_pic.hevc.desc->pic;
+   if (!enc->enc_pic.has_dependent_slice_instructions)
+      pps.dependent_slice_segments_enabled_flag = 1;
+   pps.constrained_intra_pred_flag = enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag;
+   pps.transform_skip_enabled_flag = !enc->enc_pic.hevc_spec_misc.transform_skip_disabled;
+   pps.cu_qp_delta_enabled_flag = enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag;
+   pps.pps_beta_offset_div2 = enc->enc_pic.hevc_deblock.beta_offset_div2;
+   pps.pps_tc_offset_div2 = enc->enc_pic.hevc_deblock.tc_offset_div2;
+
    struct radeon_bitstream bs;
-   struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.hevc.desc->pic;
-
    radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_set_emulation_prevention(&bs, false);
-   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
-   radeon_bs_code_fixed_bits(&bs, 0x4401, 16);
-   radeon_bs_set_emulation_prevention(&bs, true);
-   radeon_bs_code_ue(&bs, 0x0); /* pps_pic_parameter_set_id */
-   radeon_bs_code_ue(&bs, 0x0); /* pps_seq_parameter_set_id */
-   unsigned dependent_slice_segments_enabled_flag =
-      enc->enc_pic.has_dependent_slice_instructions ? pps->dependent_slice_segments_enabled_flag : 0x1;
-   radeon_bs_code_fixed_bits(&bs, dependent_slice_segments_enabled_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, pps->output_flag_present_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 3); /* num_extra_slice_header_bits */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* sign_data_hiding_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* cabac_init_present_flag */
-   radeon_bs_code_ue(&bs, pps->num_ref_idx_l0_default_active_minus1);
-   radeon_bs_code_ue(&bs, pps->num_ref_idx_l1_default_active_minus1);
-   radeon_bs_code_se(&bs, 0x0); /* init_qp_minus26 */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, !enc->enc_pic.hevc_spec_misc.transform_skip_disabled, 1);
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag, 1);
-   if (enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag)
-      radeon_bs_code_ue(&bs, 0); /* diff_cu_qp_delta_depth */
-   radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cb_qp_offset);
-   radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cr_qp_offset);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_slice_chroma_qp_offsets_present_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_pred_flag + weighted_bipred_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* transquant_bypass_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* tiles_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* entropy_coding_sync_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* deblocking_filter_control_present_flag */
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* deblocking_filter_override_enabled_flag */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
-
-   if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
-      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.beta_offset_div2);
-      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.tc_offset_div2);
-   }
-
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* pps_scaling_list_data_present_flag */
-   radeon_bs_code_fixed_bits(&bs, pps->lists_modification_present_flag, 1);
-   radeon_bs_code_ue(&bs, pps->log2_parallel_merge_level_minus2);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 2);
-
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
-   radeon_bs_byte_align(&bs);
-
+   radeon_bs_hevc_pps(&bs, &pps);
    return bs.bits_output / 8;
 }
 
 unsigned int radeon_enc_write_vps(struct radeon_encoder *enc, uint8_t *out)
 {
    struct radeon_bitstream bs;
-   struct pipe_h265_enc_vid_param *vps = &enc->enc_pic.hevc.desc->vid;
-   int i;
-
    radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_set_emulation_prevention(&bs, false);
-   radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
-   radeon_bs_code_fixed_bits(&bs, 0x4001, 16);
-   radeon_bs_set_emulation_prevention(&bs, true);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 4); /* vps_video_parameter_set_id*/
-   radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_internal_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, vps->vps_base_layer_available_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layers_minus1 */
-   radeon_bs_code_fixed_bits(&bs, vps->vps_max_sub_layers_minus1, 3);
-   radeon_bs_code_fixed_bits(&bs, vps->vps_temporal_id_nesting_flag, 1);
-   radeon_bs_code_fixed_bits(&bs, 0xffff, 16); /* vps_reserved_0xffff_16bits */
-   radeon_bs_hevc_profile_tier_level(&bs, vps->vps_max_sub_layers_minus1, &vps->profile_tier_level);
-   radeon_bs_code_fixed_bits(&bs, vps->vps_sub_layer_ordering_info_present_flag, 1);
-   i = vps->vps_sub_layer_ordering_info_present_flag ? 0 : vps->vps_max_sub_layers_minus1;
-   for (; i <= vps->vps_max_sub_layers_minus1; i++) {
-      radeon_bs_code_ue(&bs, vps->vps_max_dec_pic_buffering_minus1[i]);
-      radeon_bs_code_ue(&bs, vps->vps_max_num_reorder_pics[i]);
-      radeon_bs_code_ue(&bs, vps->vps_max_latency_increase_plus1[i]);
-   }
-   radeon_bs_code_fixed_bits(&bs, 0x0, 6); /* vps_max_layer_id */
-   radeon_bs_code_ue(&bs, 0x0); /* vps_num_layer_sets_minus1 */
-   radeon_bs_code_fixed_bits(&bs, vps->vps_timing_info_present_flag, 1);
-   if (vps->vps_timing_info_present_flag) {
-      radeon_bs_code_fixed_bits(&bs, vps->vps_num_units_in_tick, 32);
-      radeon_bs_code_fixed_bits(&bs, vps->vps_time_scale, 32);
-      radeon_bs_code_fixed_bits(&bs, vps->vps_poc_proportional_to_timing_flag, 1);
-      if (vps->vps_poc_proportional_to_timing_flag)
-         radeon_bs_code_ue(&bs, vps->vps_num_ticks_poc_diff_one_minus1);
-      radeon_bs_code_ue(&bs, 0x0); /* vps_num_hrd_parameters */
-   }
-   radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* vps_extension_flag */
-
-   radeon_bs_code_fixed_bits(&bs, 0x1, 1);
-   radeon_bs_byte_align(&bs);
-
+   radeon_bs_hevc_vps(&bs, &enc->enc_pic.hevc.desc->vid);
    return bs.bits_output / 8;
 }
 
@@ -898,7 +573,8 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
       }
       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
          radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* mvd_l1_zero_flag */
-      radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
+      if (pps->cabac_init_present_flag)
+         radeon_bs_code_fixed_bits(&bs, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
       radeon_bs_code_ue(&bs, 5 - slice->max_num_merge_cand);
    }
 
@@ -911,6 +587,22 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
    inst_index++;
 
+   if (pps->pps_slice_chroma_qp_offsets_present_flag) {
+      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cb_qp_offset);
+      radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.cr_qp_offset);
+   }
+
+   if (pps->deblocking_filter_override_enabled_flag)
+      radeon_bs_code_fixed_bits(&bs, slice->deblocking_filter_override_flag, 1);
+
+   if (slice->deblocking_filter_override_flag) {
+      radeon_bs_code_fixed_bits(&bs, slice->slice_deblocking_filter_disabled_flag, 1);
+      if (!slice->slice_deblocking_filter_disabled_flag) {
+         radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.beta_offset_div2);
+         radeon_bs_code_se(&bs, enc->enc_pic.hevc_deblock.tc_offset_div2);
+      }
+   }
+
    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
         !enc->enc_pic.hevc_deblock.disable_sao)) {
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
index 9a8a8e35c9d..97edcc42a44 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc_4_0.c
@@ -178,199 +178,14 @@ void radeon_enc_av1_obu_header(struct radeon_encoder *enc, struct radeon_bitstre
 
 unsigned int radeon_enc_write_sequence_header(struct radeon_encoder *enc, uint8_t *obu_bytes, uint8_t *out)
 {
+   struct pipe_av1_enc_seq_param seq = enc->enc_pic.av1.desc->seq;
+   seq.pic_width_in_luma_samples = enc->enc_pic.av1.coded_width;
+   seq.pic_height_in_luma_samples = enc->enc_pic.av1.coded_height;
+   seq.seq_bits.disable_screen_content_tools = enc->enc_pic.disable_screen_content_tools;
+
    struct radeon_bitstream bs;
-   uint8_t *size_offset;
-   uint32_t obu_size;
-   uint32_t width_bits;
-   uint32_t height_bits;
-   struct pipe_av1_enc_seq_param *seq = &enc->enc_pic.av1.desc->seq;
-
    radeon_bs_reset(&bs, out, NULL);
-   radeon_bs_code_fixed_bits(&bs, obu_bytes[0], 8);
-   if (obu_bytes[0] & 0x4) /* obu_extension_flag */
-      radeon_bs_code_fixed_bits(&bs, obu_bytes[1], 8);
-
-   /* obu_size, use one byte for header, the size will be written in afterwards */
-   size_offset = &out[bs.bits_output / 8];
-   radeon_bs_code_fixed_bits(&bs, 0, 8);
-
-   /* sequence_header_obu() */
-   /*  seq_profile  */
-   radeon_bs_code_fixed_bits(&bs, seq->profile, 3);
-   /*  still_picture */
-   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.still_picture, 1);
-   /*  reduced_still_picture_header */
-   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.reduced_still_picture_header, 1);
-
-   if (seq->seq_bits.reduced_still_picture_header) {
-      /*  seq_level_idx[0]  */
-      radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[0], 5);
-   } else {
-      /*  timing_info_present_flag  */
-      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.timing_info_present_flag, 1);
-
-      if (seq->seq_bits.timing_info_present_flag) {
-         /*  num_units_in_display_tick  */
-         radeon_bs_code_fixed_bits(&bs, seq->num_units_in_display_tick, 32);
-         /*  time_scale  */
-         radeon_bs_code_fixed_bits(&bs, seq->time_scale, 32);
-         /*  equal_picture_interval  */
-         radeon_bs_code_fixed_bits(&bs, seq->seq_bits.equal_picture_interval, 1);
-         /*  num_ticks_per_picture_minus_1  */
-          if (seq->seq_bits.equal_picture_interval)
-              radeon_bs_code_uvlc(&bs, seq->num_tick_per_picture_minus1);
-          /*  decoder_model_info_present_flag  */
-          radeon_bs_code_fixed_bits(&bs, seq->seq_bits.decoder_model_info_present_flag, 1);
-          if (seq->seq_bits.decoder_model_info_present_flag) {
-             /*  buffer_delay_length_minus1  */
-             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_delay_length_minus1, 5);
-             /*  num_units_in_decoding_tick  */
-             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.num_units_in_decoding_tick, 32);
-             /*  buffer_removal_time_length_minus1  */
-             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.buffer_removal_time_length_minus1, 5);
-             /*  frame_presentation_time_length_minus1  */
-             radeon_bs_code_fixed_bits(&bs, seq->decoder_model_info.frame_presentation_time_length_minus1, 5);
-          }
-      }
-
-      /*  initial_display_delay_present_flag  */
-      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.initial_display_delay_present_flag, 1);
-      /*  operating_points_cnt_minus_1  */
-      radeon_bs_code_fixed_bits(&bs, seq->num_temporal_layers - 1, 5);
-
-      for (uint32_t i = 0; i < seq->num_temporal_layers; i++) {
-         /*  operating_point_idc[i]  */
-         radeon_bs_code_fixed_bits(&bs, seq->operating_point_idc[i], 12);
-         /*  seq_level_idx[i]  */
-         radeon_bs_code_fixed_bits(&bs, seq->seq_level_idx[i], 5);
-         if (seq->seq_level_idx[i] > 7)
-            /*  seq_tier[i]  */
-            radeon_bs_code_fixed_bits(&bs, seq->seq_tier[i], 1);
-         if (seq->seq_bits.decoder_model_info_present_flag) {
-            /*  decoder_model_present_for_this_op[i]  */
-            radeon_bs_code_fixed_bits(&bs, seq->decoder_model_present_for_this_op[i], 1);
-            if (seq->decoder_model_present_for_this_op[i]) {
-               uint32_t length = seq->decoder_model_info.buffer_delay_length_minus1 + 1;
-               /*  decoder_buffer_delay[i]  */
-               radeon_bs_code_fixed_bits(&bs, seq->decoder_buffer_delay[i], length);
-               /*  encoder_buffer_delay[i]  */
-               radeon_bs_code_fixed_bits(&bs, seq->encoder_buffer_delay[i], length);
-               /*  low_delay_mode_flag[i]  */
-               radeon_bs_code_fixed_bits(&bs, seq->low_delay_mode_flag[i], 1);
-            }
-         }
-         if (seq->seq_bits.initial_display_delay_present_flag) {
-            /*  initial_display_delay_present_for_this_op[i]  */
-            radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_present_for_this_op[i], 1);
-            if (seq->initial_display_delay_present_for_this_op[i])
-               /*  initial_display_delay_minus_1[i]  */
-               radeon_bs_code_fixed_bits(&bs, seq->initial_display_delay_minus_1[i], 4);
-         }
-      }
-   }
-
-   /*  frame_width_bits_minus_1  */
-   width_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_width);
-   radeon_bs_code_fixed_bits(&bs, width_bits - 1, 4);
-   /*  frame_height_bits_minus_1  */
-   height_bits = radeon_enc_value_bits(enc->enc_pic.av1.coded_height);
-   radeon_bs_code_fixed_bits(&bs, height_bits - 1, 4);
-   /*  max_frame_width_minus_1  */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_width - 1,
-                                   width_bits);
-   /*  max_frame_height_minus_1  */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1.coded_height - 1,
-                                   height_bits);
-
-   if (!seq->seq_bits.reduced_still_picture_header)
-      /*  frame_id_numbers_present_flag  */
-      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.frame_id_number_present_flag, 1);
-
-   if (seq->seq_bits.frame_id_number_present_flag) {
-      /*  delta_frame_id_length_minus_2  */
-      radeon_bs_code_fixed_bits(&bs, seq->delta_frame_id_length - 2, 4);
-      /*  additional_frame_id_length_minus_1  */
-      radeon_bs_code_fixed_bits(&bs, seq->additional_frame_id_length - 1, 3);
-   }
-
-   /*  use_128x128_superblock  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-   /*  enable_filter_intra  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-   /*  enable_intra_edge_filter  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-
-   if (!seq->seq_bits.reduced_still_picture_header) {
-      /*  enable_interintra_compound  */
-      radeon_bs_code_fixed_bits(&bs, 0, 1);
-      /*  enable_masked_compound  */
-      radeon_bs_code_fixed_bits(&bs, 0, 1);
-      /*  enable_warped_motion  */
-      radeon_bs_code_fixed_bits(&bs, 0, 1);
-      /*  enable_dual_filter  */
-      radeon_bs_code_fixed_bits(&bs, 0, 1);
-      /*  enable_order_hint  */
-      radeon_bs_code_fixed_bits(&bs, seq->seq_bits.enable_order_hint, 1);
-
-      if (seq->seq_bits.enable_order_hint) {
-         /*  enable_jnt_comp  */
-         radeon_bs_code_fixed_bits(&bs, 0, 1);
-         /*  enable_ref_frame_mvs  */
-         radeon_bs_code_fixed_bits(&bs, 0, 1);
-      }
-
-      /*  seq_choose_screen_content_tools  */
-      radeon_bs_code_fixed_bits(&bs, enc->enc_pic.disable_screen_content_tools ? 0 : 1, 1);
-      if (enc->enc_pic.disable_screen_content_tools)
-         /*  seq_force_screen_content_tools  */
-         radeon_bs_code_fixed_bits(&bs, 0, 1);
-      else
-         /*  seq_choose_integer_mv  */
-         radeon_bs_code_fixed_bits(&bs, 1, 1);
-
-      if (seq->seq_bits.enable_order_hint)
-         /*  order_hint_bits_minus_1  */
-         radeon_bs_code_fixed_bits(&bs, seq->order_hint_bits - 1, 3);
-   }
-
-   /*  enable_superres  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-   /*  enable_cdef  */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.av1_spec_misc.cdef_mode ? 1 : 0, 1);
-   /*  enable_restoration  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-   /*  high_bitdepth  */
-   radeon_bs_code_fixed_bits(&bs, enc->enc_pic.enc_output_format.output_color_bit_depth, 1);
-   /*  mono_chrome  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-   /*  color_description_present_flag  */
-   radeon_bs_code_fixed_bits(&bs, seq->seq_bits.color_description_present_flag, 1);
-
-   if (seq->seq_bits.color_description_present_flag) {
-      /*  color_primaries  */
-      radeon_bs_code_fixed_bits(&bs, seq->color_config.color_primaries, 8);
-      /*  transfer_characteristics  */
-      radeon_bs_code_fixed_bits(&bs, seq->color_config.transfer_characteristics, 8);
-      /*  matrix_coefficients  */
-      radeon_bs_code_fixed_bits(&bs, seq->color_config.matrix_coefficients, 8);
-   }
-   /*  color_range  */
-   radeon_bs_code_fixed_bits(&bs, seq->color_config.color_range, 1);
-   /*  chroma_sample_position  */
-   radeon_bs_code_fixed_bits(&bs, seq->color_config.chroma_sample_position, 2);
-   /*  separate_uv_delta_q  */
-   bool separate_delta_q = false;
-   radeon_bs_code_fixed_bits(&bs, !!(separate_delta_q), 1);
-   /*  film_grain_params_present  */
-   radeon_bs_code_fixed_bits(&bs, 0, 1);
-
-   /*  trailing_one_bit  */
-   radeon_bs_code_fixed_bits(&bs, 1, 1);
-   radeon_bs_byte_align(&bs);
-
-   obu_size = (uint32_t)(&out[bs.bits_output / 8] - size_offset - 1);
-   radeon_enc_code_leb128(size_offset, obu_size, 1);
-
+   radeon_bs_av1_seq(&bs, obu_bytes, &seq);
    return bs.bits_output / 8;
 }