diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 890360b5aa6..1449b68c134 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -200,7 +200,7 @@ uint32_t genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, const VkShaderStageFlags dirty, - struct anv_shader_bin **shaders, + const struct anv_shader_bin **shaders, uint32_t num_shaders); void genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 02ce1c6c9e9..6673b6def14 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -3165,7 +3165,7 @@ struct anv_descriptor_set { }; static inline bool -anv_descriptor_set_is_push(struct anv_descriptor_set *set) +anv_descriptor_set_is_push(const struct anv_descriptor_set *set) { return set->pool == NULL; } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 57b35b7610e..afb0cd967c4 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1937,7 +1937,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) static inline struct anv_state emit_dynamic_buffer_binding_table_entry(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, - struct anv_pipeline_binding *binding, + const struct anv_pipeline_binding *binding, const struct anv_descriptor *desc) { if (!desc->buffer) @@ -1985,7 +1985,7 @@ emit_dynamic_buffer_binding_table_entry(struct anv_cmd_buffer *cmd_buffer, static uint32_t emit_indirect_descriptor_binding_table_entry(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, - struct anv_pipeline_binding *binding, + const struct anv_pipeline_binding *binding, const struct anv_descriptor *desc) { struct anv_device *device = cmd_buffer->device; @@ -2079,7 +2079,7 @@ static uint32_t emit_direct_descriptor_binding_table_entry(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, const struct anv_descriptor_set *set, - struct anv_pipeline_binding *binding, + const struct anv_pipeline_binding *binding, const struct anv_descriptor *desc) { uint32_t desc_offset; @@ -2120,12 +2120,12 @@ emit_direct_descriptor_binding_table_entry(struct anv_cmd_buffer *cmd_buffer, static VkResult emit_binding_table(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, - struct anv_shader_bin *shader, + const struct anv_shader_bin *shader, struct anv_state *bt_state) { uint32_t state_offset; - struct anv_pipeline_bind_map *map = &shader->bind_map; + const struct anv_pipeline_bind_map *map = &shader->bind_map; if (map->surface_count == 0) { *bt_state = (struct anv_state) { 0, }; return VK_SUCCESS; @@ -2140,7 +2140,8 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, return VK_ERROR_OUT_OF_DEVICE_MEMORY; for (uint32_t s = 0; s < map->surface_count; s++) { - struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s]; + const struct anv_pipeline_binding *binding = + &map->surface_to_descriptor[s]; struct anv_state surface_state; @@ -2198,7 +2199,7 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, default: { assert(binding->set < MAX_SETS); - const struct anv_descriptor_set *set = + struct anv_descriptor_set *set = pipe_state->descriptors[binding->set]; if (binding->index >= set->descriptor_count) { @@ -2266,10 +2267,10 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, static VkResult emit_samplers(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, - struct anv_shader_bin *shader, + const struct anv_shader_bin *shader, struct anv_state *state) { - struct anv_pipeline_bind_map *map = &shader->bind_map; + const struct anv_pipeline_bind_map *map = &shader->bind_map; if (map->sampler_count == 0) { *state = (struct anv_state) { 0, }; return VK_SUCCESS; @@ -2282,7 +2283,8 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer, return VK_ERROR_OUT_OF_DEVICE_MEMORY; for (uint32_t s = 0; s < map->sampler_count; s++) { - struct anv_pipeline_binding *binding = &map->sampler_to_descriptor[s]; + const struct anv_pipeline_binding *binding = + &map->sampler_to_descriptor[s]; const struct anv_descriptor *desc = &pipe_state->descriptors[binding->set]->descriptors[binding->index]; @@ -2309,7 +2311,7 @@ uint32_t genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_pipeline_state *pipe_state, const VkShaderStageFlags dirty, - struct anv_shader_bin **shaders, + const struct anv_shader_bin **shaders, uint32_t num_shaders) { VkShaderStageFlags flushed = 0; diff --git a/src/intel/vulkan/genX_cmd_compute.c b/src/intel/vulkan/genX_cmd_compute.c index 8971b26a3b6..3b06f5a0041 100644 --- a/src/intel/vulkan/genX_cmd_compute.c +++ b/src/intel/vulkan/genX_cmd_compute.c @@ -174,10 +174,11 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) || cmd_buffer->state.compute.pipeline_dirty) { - genX(cmd_buffer_flush_descriptor_sets)(cmd_buffer, - &cmd_buffer->state.compute.base, - VK_SHADER_STAGE_COMPUTE_BIT, - &pipeline->cs, 1); + genX(cmd_buffer_flush_descriptor_sets)( + cmd_buffer, + &cmd_buffer->state.compute.base, + VK_SHADER_STAGE_COMPUTE_BIT, + (const struct anv_shader_bin **)&pipeline->cs, 1); cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT; #if GFX_VERx10 < 125 diff --git a/src/intel/vulkan/genX_cmd_draw.c b/src/intel/vulkan/genX_cmd_draw.c index 095e9dd5be4..d849d5aa212 100644 --- a/src/intel/vulkan/genX_cmd_draw.c +++ b/src/intel/vulkan/genX_cmd_draw.c @@ -919,7 +919,7 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer) cmd_buffer, &cmd_buffer->state.gfx.base, descriptors_dirty, - pipeline->base.shaders, + (const struct anv_shader_bin **)pipeline->base.shaders, ARRAY_SIZE(pipeline->base.shaders)); cmd_buffer->state.descriptors_dirty &= ~dirty; }