From 092186d9857e81f5f4c4f3c3a8820cb2d1a57b9a Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Wed, 4 Nov 2020 17:48:21 -0500 Subject: [PATCH] util/threaded_context: use driver's buffer alignment for staging transfers this coincidentally worked because radeonsi has a hardcoded value of 64, but other drivers do not use this value and then things are subtly broken Reviewed-by: Adam Jackson Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/auxiliary/util/u_threaded_context.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/util/u_threaded_context.c b/src/gallium/auxiliary/util/u_threaded_context.c index 093f9d594d5..1eaff77724e 100644 --- a/src/gallium/auxiliary/util/u_threaded_context.c +++ b/src/gallium/auxiliary/util/u_threaded_context.c @@ -1566,7 +1566,8 @@ tc_transfer_map(struct pipe_context *_pipe, u_upload_alloc(tc->base.stream_uploader, 0, box->width + (box->x % tc->map_buffer_alignment), - 64, &ttrans->offset, &ttrans->staging, (void**)&map); + tc->map_buffer_alignment, &ttrans->offset, + &ttrans->staging, (void**)&map); if (!map) { slab_free(&tc->pool_transfers, ttrans); return NULL;