From 07eab4ab40a5ad972814e2e40c684f80458ed27a Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Wed, 31 Jan 2024 18:44:21 +0000 Subject: [PATCH] aco: require linear vgpr uses to be late kill MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This also removes some linear VGPR tests which will be replaced soon anyway. fossil-db (navi31): Totals from 107 (0.14% of 79242) affected shaders: Instrs: 66203 -> 66211 (+0.01%); split: -0.09%, +0.10% CodeSize: 354644 -> 354588 (-0.02%); split: -0.08%, +0.07% VGPRs: 4476 -> 4452 (-0.54%); split: -0.80%, +0.27% Latency: 513863 -> 513877 (+0.00%); split: -0.08%, +0.08% InvThroughput: 68871 -> 68870 (-0.00%); split: -0.02%, +0.02% SClause: 1589 -> 1590 (+0.06%) PreVGPRs: 3404 -> 3415 (+0.32%) Signed-off-by: Rhys Perry Reviewed-by: Daniel Schürmann Part-of: --- .../compiler/aco_instruction_selection.cpp | 12 +- src/amd/compiler/aco_reduce_assign.cpp | 10 +- src/amd/compiler/aco_spill.cpp | 6 +- src/amd/compiler/aco_validate.cpp | 10 ++ src/amd/compiler/tests/test_d3d11_derivs.cpp | 50 ++++----- src/amd/compiler/tests/test_reduce_assign.cpp | 4 +- src/amd/compiler/tests/test_regalloc.cpp | 103 ------------------ 7 files changed, 59 insertions(+), 136 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 9a56ca2c68c..4c00d971a0c 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -6095,8 +6095,11 @@ emit_mimg(Builder& bld, aco_opcode op, Temp dst, Temp rsrc, Operand samp, std::v mimg->operands[0] = Operand(rsrc); mimg->operands[1] = samp; mimg->operands[2] = vdata; - for (unsigned i = 0; i < coords.size(); i++) + for (unsigned i = 0; i < coords.size(); i++) { mimg->operands[3 + i] = Operand(coords[i]); + if (coords[i].regClass().is_linear_vgpr()) + mimg->operands[3 + i].setLateKill(true); + } mimg->strict_wqm = strict_wqm; MIMG_instruction* res = mimg.get(); @@ -10320,8 +10323,11 @@ visit_block(isel_context* ctx, nir_block* block) { if (ctx->block->kind & block_kind_top_level) { Builder bld(ctx->program, ctx->block); - for (Temp tmp : ctx->unended_linear_vgprs) - bld.pseudo(aco_opcode::p_end_linear_vgpr, tmp); + for (Temp tmp : ctx->unended_linear_vgprs) { + Operand op(tmp); + op.setLateKill(true); + bld.pseudo(aco_opcode::p_end_linear_vgpr, op); + } ctx->unended_linear_vgprs.clear(); } diff --git a/src/amd/compiler/aco_reduce_assign.cpp b/src/amd/compiler/aco_reduce_assign.cpp index 55fc525e485..bffeb81c35c 100644 --- a/src/amd/compiler/aco_reduce_assign.cpp +++ b/src/amd/compiler/aco_reduce_assign.cpp @@ -82,8 +82,11 @@ setup_reduce_temp(Program* program) aco_ptr end{create_instruction( aco_opcode::p_end_linear_vgpr, Format::PSEUDO, vtmp_inserted_at >= 0 ? 2 : 1, 0)}; end->operands[0] = Operand(reduceTmp); - if (vtmp_inserted_at >= 0) + end->operands[0].setLateKill(true); + if (vtmp_inserted_at >= 0) { end->operands[1] = Operand(vtmp); + end->operands[1].setLateKill(true); + } /* insert after the phis of the block */ std::vector>::iterator it = block.instructions.begin(); while ((*it)->opcode == aco_opcode::p_linear_phi || (*it)->opcode == aco_opcode::p_phi) @@ -169,8 +172,11 @@ setup_reduce_temp(Program* program) if (instr->isReduction()) { instr->operands[1] = Operand(reduceTmp); - if (need_vtmp) + instr->operands[1].setLateKill(true); + if (need_vtmp) { instr->operands[2] = Operand(vtmp); + instr->operands[2].setLateKill(true); + } } else { assert(instr->opcode == aco_opcode::p_interp_gfx11 || instr->opcode == aco_opcode::p_bpermute_permlane); diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp index 8da3d49202b..2f9e4b0421f 100644 --- a/src/amd/compiler/aco_spill.cpp +++ b/src/amd/compiler/aco_spill.cpp @@ -1742,8 +1742,10 @@ end_unused_spill_vgprs(spill_ctx& ctx, Block& block, std::vector& vgpr_spi aco_ptr destr{create_instruction( aco_opcode::p_end_linear_vgpr, Format::PSEUDO, temps.size(), 0)}; - for (unsigned i = 0; i < temps.size(); i++) + for (unsigned i = 0; i < temps.size(); i++) { destr->operands[i] = Operand(temps[i]); + destr->operands[i].setLateKill(true); + } std::vector>::iterator it = block.instructions.begin(); while (is_phi(*it)) @@ -1856,6 +1858,7 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) Pseudo_instruction* spill = create_instruction(aco_opcode::p_spill, Format::PSEUDO, 3, 0); spill->operands[0] = Operand(vgpr_spill_temps[spill_slot / ctx.wave_size]); + spill->operands[0].setLateKill(true); spill->operands[1] = Operand::c32(spill_slot % ctx.wave_size); spill->operands[2] = (*it)->operands[0]; instructions.emplace_back(aco_ptr(spill)); @@ -1896,6 +1899,7 @@ assign_spill_slots(spill_ctx& ctx, unsigned spills_to_vgpr) Pseudo_instruction* reload = create_instruction( aco_opcode::p_reload, Format::PSEUDO, 2, 1); reload->operands[0] = Operand(vgpr_spill_temps[spill_slot / ctx.wave_size]); + reload->operands[0].setLateKill(true); reload->operands[1] = Operand::c32(spill_slot % ctx.wave_size); reload->definitions[0] = (*it)->definitions[0]; instructions.emplace_back(aco_ptr(reload)); diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 5d59b0af565..d8d88fbdee6 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -384,6 +384,16 @@ validate_ir(Program* program) } } + /* Check that linear vgprs are late kill: this is to ensure linear VGPR operands and + * normal VGPR definitions don't try to use the same register, which is problematic + * because of assignment restrictions. + */ + for (Operand& op : instr->operands) { + if (!op.isUndefined() && !op.isFixed() && op.hasRegClass() && + op.regClass().is_linear_vgpr()) + check(op.isLateKill(), "Linear VGPR operands must be late kill", instr.get()); + } + /* check subdword definitions */ for (unsigned i = 0; i < instr->definitions.size(); i++) { if (instr->definitions[i].regClass().is_subdword()) diff --git a/src/amd/compiler/tests/test_d3d11_derivs.cpp b/src/amd/compiler/tests/test_d3d11_derivs.cpp index f180de4a157..0b68803f979 100644 --- a/src/amd/compiler/tests/test_d3d11_derivs.cpp +++ b/src/amd/compiler/tests/test_d3d11_derivs.cpp @@ -54,10 +54,10 @@ BEGIN_TEST(d3d11_derivs.simple) //>> v1: %y = v_interp_p2_f32 (kill)%_, (kill)%_:m0, (kill)%_ attr0.y //>> lv2: %wqm = p_start_linear_vgpr (kill)%x, (kill)%y //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2d + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rx_tmp, v#_, attr0.x ; $_ @@ -95,10 +95,10 @@ BEGIN_TEST(d3d11_derivs.constant) //>> v1: %x = v_interp_p2_f32 (kill)%_, (kill)%_:m0, (kill)%_ attr0.x //>> lv2: %wqm = p_start_linear_vgpr (kill)%x, -0.5 //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2d + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rx, v#_, attr0.x ; $_ @@ -136,7 +136,7 @@ BEGIN_TEST(d3d11_derivs.discard) //>> s2: %_:exec, s1: (kill)%_:scc = s_andn2_b64 %_:exec, %_ //>> s2: %_, s1: %_:scc = s_andn2_b64 (kill)%_, (kill)%_ //>> p_exit_early_if (kill)%_:scc - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (kill)%wqm 2d + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)(kill)%wqm 2d pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); END_TEST @@ -167,10 +167,10 @@ BEGIN_TEST(d3d11_derivs.bias) //>> s2: %_:s[0-1], s1: %_:s[2], s1: %_:s[3], s1: %_:s[4], v2: %_:v[0-1], v1: %bias:v[2] = p_startpgm //>> lv3: %wqm = p_start_linear_vgpr v1: undef, (kill)%_, (kill)%_ //>> BB1 - //>> v4: %_ = image_sample_b (kill)%_, (kill)%_, v1: undef, %wqm, (kill)%bias 2d + //>> v4: %_ = image_sample_b (kill)%_, (kill)%_, v1: undef, (latekill)%wqm, (kill)%bias 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rx_tmp, v#_, attr0.x ; $_ @@ -210,10 +210,10 @@ BEGIN_TEST(d3d11_derivs.offset) //>> lv3: %wqm = p_start_linear_vgpr v1: undef, (kill)%_, (kill)%_ //>> BB1 //>> v1: %offset = p_parallelcopy 0x201 - //>> v4: %_ = image_sample_o (kill)%_, (kill)%_, v1: undef, %wqm, (kill)%offset 2d + //>> v4: %_ = image_sample_o (kill)%_, (kill)%_, v1: undef, (latekill)%wqm, (kill)%offset 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rx_tmp, v#_, attr0.x ; $_ @@ -255,10 +255,10 @@ BEGIN_TEST(d3d11_derivs.array) //>> v1: %layer = v_rndne_f32 (kill)%_ //>> lv3: %wqm = p_start_linear_vgpr (kill)%_, (kill)%_, (kill)%layer //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2darray da + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2darray da //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rl_tmp, v#_, attr0.z ; $_ @@ -302,10 +302,10 @@ BEGIN_TEST(d3d11_derivs.bias_array) //>> v1: %layer = v_rndne_f32 (kill)%_ //>> lv4: %wqm = p_start_linear_vgpr v1: undef, (kill)%_, (kill)%_, (kill)%layer //>> BB1 - //>> v4: %_ = image_sample_b (kill)%_, (kill)%_, v1: undef, %wqm, (kill)%bias 2darray da + //>> v4: %_ = image_sample_b (kill)%_, (kill)%_, v1: undef, (latekill)%wqm, (kill)%bias 2darray da //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rl_tmp, v#_, attr0.z ; $_ @@ -347,10 +347,10 @@ BEGIN_TEST(d3d11_derivs._1d_gfx9) //>> v1: %x = v_interp_p2_f32 (kill)%_, (kill)%_:m0, (kill)%_ attr0.x //>> lv2: %wqm = p_start_linear_vgpr (kill)%x, 0.5 //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2d + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rx, v#_, attr0.x ; $_ @@ -388,10 +388,10 @@ BEGIN_TEST(d3d11_derivs._1d_array_gfx9) //>> v1: %x = v_interp_p2_f32 (kill)%_, (kill)%_:m0, (kill)%_ attr0.x //>> lv3: %wqm = p_start_linear_vgpr (kill)%x, 0.5, (kill)%layer //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2darray da + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2darray da //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_interp_p2_f32_e32 v#rl_tmp, v#_, attr0.y ; $_ @@ -435,10 +435,10 @@ BEGIN_TEST(d3d11_derivs.cube) //>> v1: %y = v_fmaak_f32 (kill)%_, (kill)%_, 0x3fc00000 //>> lv3: %wqm = p_start_linear_vgpr (kill)%x, (kill)%y, (kill)%face //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm cube da + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm cube da //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_cubeid_f32 v#rf_tmp, v#_, v#_, v#_ ; $_ $_ @@ -482,10 +482,10 @@ BEGIN_TEST(d3d11_derivs.cube_array) //>> v1: %face_layer = v_fmamk_f32 (kill)%layer, (kill)%face, 0x41000000 //>> lv3: %wqm = p_start_linear_vgpr (kill)%x, (kill)%y, (kill)%face_layer //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm cube da + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm cube da //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); //>> v_rndne_f32_e32 v#rl, v#_ ; $_ @@ -563,10 +563,10 @@ BEGIN_TEST(d3d11_derivs.bc_optimize) //>> v1: %y = v_interp_p2_f32 (kill)%y_coord2, (kill)%_:m0, (kill)%_ attr0.y //>> lv2: %wqm = p_start_linear_vgpr (kill)%x, (kill)%y //>> BB1 - //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, %wqm 2d + //>> v4: %_ = image_sample (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); END_TEST @@ -604,10 +604,10 @@ BEGIN_TEST(d3d11_derivs.get_lod) //>> v1: %y1_m_y0 = v_sub_f32 %y, %y0 quad_perm:[1,1,1,1] bound_ctrl:1 fi //>> v1: %y2_m_y0 = v_sub_f32 (kill)%y, (kill)%y0 quad_perm:[2,2,2,2] bound_ctrl:1 fi //>> BB1 - //>> v2: %_ = image_get_lod (kill)%_, (kill)%_, v1: undef, %wqm 2d + //>> v2: %_ = image_get_lod (kill)%_, (kill)%_, v1: undef, (latekill)%wqm 2d //>> BB2 //>> BB6 - //>> p_end_linear_vgpr (kill)%wqm + //>> p_end_linear_vgpr (latekill)(kill)%wqm pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR"); END_TEST diff --git a/src/amd/compiler/tests/test_reduce_assign.cpp b/src/amd/compiler/tests/test_reduce_assign.cpp index 7f44e55486f..7f6b4644803 100644 --- a/src/amd/compiler/tests/test_reduce_assign.cpp +++ b/src/amd/compiler/tests/test_reduce_assign.cpp @@ -46,7 +46,7 @@ BEGIN_TEST(setup_reduce_temp.divergent_if_phi) program.get(), bld, Operand(inputs[0]), [&]() -> void { - //>> s1: %_, s2: %_, s1: %_:scc = p_reduce %a, %lv, lv1: undef op:umin32 cluster_size:64 + //>> s1: %_, s2: %_, s1: %_:scc = p_reduce %a, (latekill)%lv, lv1: undef op:umin32 cluster_size:64 Instruction* reduce = bld.reduction(aco_opcode::p_reduce, bld.def(s1), bld.def(bld.lm), bld.def(s1, scc), inputs[1], Operand(v1.as_linear()), Operand(v1.as_linear()), umin32); @@ -58,7 +58,7 @@ BEGIN_TEST(setup_reduce_temp.divergent_if_phi) }); bld.pseudo(aco_opcode::p_phi, bld.def(v1), Operand::c32(1), Operand::zero()); //>> /* logical preds: BB1, BB4, / linear preds: BB4, BB5, / kind: uniform, top-level, merge, */ - //! p_end_linear_vgpr %lv + //! p_end_linear_vgpr (latekill)%lv finish_setup_reduce_temp_test(); END_TEST diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp index 2a8ac922fc6..60f33d63028 100644 --- a/src/amd/compiler/tests/test_regalloc.cpp +++ b/src/amd/compiler/tests/test_regalloc.cpp @@ -227,109 +227,6 @@ BEGIN_TEST(regalloc.scratch_sgpr.create_vector_sgpr_operand) finish_ra_test(ra_test_policy(), true); END_TEST -BEGIN_TEST(regalloc.linear_vgpr.live_range_split.fixed_def) - //>> p_startpgm - if (!setup_cs("", GFX10)) - return; - - PhysReg reg_v0{256}; - - //! lv1: %tmp1:v[0] = p_unit_test - Temp tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1.as_linear(), reg_v0)); - - //! lv1: %tmp2:v[1] = p_parallelcopy %tmp1:v[0] - //! v1: %_:v[0] = p_unit_test - bld.pseudo(aco_opcode::p_unit_test, Definition(reg_v0, v1)); - - //! p_unit_test %tmp2:v[1] - bld.pseudo(aco_opcode::p_unit_test, tmp); - - finish_ra_test(ra_test_policy()); -END_TEST - -BEGIN_TEST(regalloc.linear_vgpr.live_range_split.get_reg_impl) - //>> p_startpgm - if (!setup_cs("", GFX10)) - return; - - program->dev.vgpr_limit = 3; - - PhysReg reg_v1{257}; - - //! s1: %scc_tmp:scc, s1: %1:s[0] = p_unit_test - Temp s0_tmp = bld.tmp(s1); - Temp scc_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(s1, scc), - Definition(s0_tmp.id(), PhysReg{0}, s1)); - - //! lv1: %tmp1:v[1] = p_unit_test - Temp tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1.as_linear(), reg_v1)); - - //! lv1: %tmp2:v[2] = p_parallelcopy %tmp1:v[1] - //! v2: %_:v[0-1] = p_unit_test - bld.pseudo(aco_opcode::p_unit_test, bld.def(v2)); - - //! p_unit_test %tmp2:v[2], %scc_tmp:scc, %1:s[0] - bld.pseudo(aco_opcode::p_unit_test, tmp, scc_tmp, s0_tmp); - - finish_ra_test(ra_test_policy()); - - //>> lv1: %5:v[2] = p_parallelcopy %3:v[1] scc:1 scratch:s1 - Pseudo_instruction& parallelcopy = program->blocks[0].instructions[3]->pseudo(); - aco_print_instr(program->gfx_level, ¶llelcopy, output); - fprintf(output, " scc:%u scratch:s%u\n", parallelcopy.tmp_in_scc, - parallelcopy.scratch_sgpr.reg()); -END_TEST - -BEGIN_TEST(regalloc.linear_vgpr.live_range_split.get_regs_for_copies) - //>> p_startpgm - if (!setup_cs("", GFX10)) - return; - - program->dev.vgpr_limit = 6; - - PhysReg reg_v2{258}; - PhysReg reg_v4{260}; - - //! lv1: %lin_tmp1:v[4] = p_unit_test - Temp lin_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1.as_linear(), reg_v4)); - //! v2: %log_tmp1:v[2-3] = p_unit_test - Temp log_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v2, reg_v2)); - - //! lv1: %lin_tmp2:v[0], v2: %log_tmp2:v[4-5] = p_parallelcopy %lin_tmp1:v[4], %log_tmp1:v[2-3] - //! v3: %_:v[1-3] = p_unit_test - bld.pseudo(aco_opcode::p_unit_test, bld.def(v3)); - - //! p_unit_test %log_tmp2:v[4-5], %lin_tmp2:v[0] - bld.pseudo(aco_opcode::p_unit_test, log_tmp, lin_tmp); - - finish_ra_test(ra_test_policy()); -END_TEST - -BEGIN_TEST(regalloc.linear_vgpr.live_range_split.get_reg_create_vector) - //>> p_startpgm - if (!setup_cs("", GFX10)) - return; - - program->dev.vgpr_limit = 4; - - PhysReg reg_v0{256}; - PhysReg reg_v1{257}; - - //! lv1: %lin_tmp1:v[0] = p_unit_test - Temp lin_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1.as_linear(), reg_v0)); - //! v1: %log_tmp:v[1] = p_unit_test - Temp log_tmp = bld.pseudo(aco_opcode::p_unit_test, bld.def(v1, reg_v1)); - - //! lv1: %lin_tmp2:v[2] = p_parallelcopy %lin_tmp1:v[0] - //! v2: %_:v[0-1] = p_create_vector v1: undef, %log_tmp:v[1] - bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(v1), log_tmp); - - //! p_unit_test %lin_tmp2:v[2] - bld.pseudo(aco_opcode::p_unit_test, lin_tmp); - - finish_ra_test(ra_test_policy()); -END_TEST - BEGIN_TEST(regalloc.branch_def_phis_at_merge_block) //>> p_startpgm if (!setup_cs("", GFX10))