From 07ca1bbb056e81cdef9d86d8799237083f13760a Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Tue, 29 Oct 2024 12:51:55 -0700 Subject: [PATCH] panvk: expand meta stage and access flags VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT is equivalent to the logical OR of: - VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT - VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT VK_ACCESS_2_SHADER_READ_BIT is equivalent to the logical OR of: - VK_ACCESS_2_SHADER_SAMPLED_READ_BIT - VK_ACCESS_2_SHADER_STORAGE_READ_BIT VK_ACCESS_2_SHADER_WRITE_BIT is equivalent to VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT. Signed-off-by: Chia-I Wu Reviewed-by: Boris Brezillon Part-of: --- src/panfrost/vulkan/csf/panvk_vX_cmd_buffer.c | 34 +++++++++---------- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/src/panfrost/vulkan/csf/panvk_vX_cmd_buffer.c b/src/panfrost/vulkan/csf/panvk_vX_cmd_buffer.c index ca5abb6cb0b..dbda37de016 100644 --- a/src/panfrost/vulkan/csf/panvk_vX_cmd_buffer.c +++ b/src/panfrost/vulkan/csf/panvk_vX_cmd_buffer.c @@ -208,9 +208,11 @@ stages_cover_subqueue(enum panvk_subqueue_id subqueue, VkPipelineStageFlags2 stages) { static const VkPipelineStageFlags2 queue_coverage[PANVK_SUBQUEUE_COUNT] = { - [PANVK_SUBQUEUE_VERTEX_TILER] = VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | - VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT | - VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT, + [PANVK_SUBQUEUE_VERTEX_TILER] = + VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | + VK_PIPELINE_STAGE_2_INDEX_INPUT_BIT | + VK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT | + VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT, [PANVK_SUBQUEUE_FRAGMENT] = VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT | @@ -254,35 +256,31 @@ collect_cache_flush_info(enum panvk_subqueue_id subqueue, VkAccessFlags2 src_access, VkAccessFlags2 dst_access) { static const VkAccessFlags2 dev_writes[PANVK_SUBQUEUE_COUNT] = { - [PANVK_SUBQUEUE_VERTEX_TILER] = VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | - VK_ACCESS_2_SHADER_WRITE_BIT | - VK_ACCESS_2_TRANSFER_WRITE_BIT, + [PANVK_SUBQUEUE_VERTEX_TILER] = + VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | VK_ACCESS_2_TRANSFER_WRITE_BIT, [PANVK_SUBQUEUE_FRAGMENT] = - VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | VK_ACCESS_2_SHADER_WRITE_BIT | + VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | VK_ACCESS_2_TRANSFER_WRITE_BIT, - [PANVK_SUBQUEUE_COMPUTE] = VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | - VK_ACCESS_2_SHADER_WRITE_BIT | - VK_ACCESS_2_TRANSFER_WRITE_BIT, + [PANVK_SUBQUEUE_COMPUTE] = + VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT | VK_ACCESS_2_TRANSFER_WRITE_BIT, }; static const VkAccessFlags2 dev_reads[PANVK_SUBQUEUE_COUNT] = { [PANVK_SUBQUEUE_VERTEX_TILER] = VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT | VK_ACCESS_2_INDEX_READ_BIT | VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT | VK_ACCESS_2_UNIFORM_READ_BIT | - VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_TRANSFER_READ_BIT | - VK_ACCESS_2_SHADER_SAMPLED_READ_BIT | + VK_ACCESS_2_TRANSFER_READ_BIT | VK_ACCESS_2_SHADER_SAMPLED_READ_BIT | VK_ACCESS_2_SHADER_STORAGE_READ_BIT, [PANVK_SUBQUEUE_FRAGMENT] = - VK_ACCESS_2_UNIFORM_READ_BIT | VK_ACCESS_2_SHADER_READ_BIT | - VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT | + VK_ACCESS_2_UNIFORM_READ_BIT | VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT | VK_ACCESS_2_TRANSFER_READ_BIT | VK_ACCESS_2_SHADER_SAMPLED_READ_BIT | VK_ACCESS_2_SHADER_STORAGE_READ_BIT, - [PANVK_SUBQUEUE_COMPUTE] = - VK_ACCESS_2_UNIFORM_READ_BIT | VK_ACCESS_2_SHADER_READ_BIT | - VK_ACCESS_2_TRANSFER_READ_BIT | VK_ACCESS_2_SHADER_SAMPLED_READ_BIT | - VK_ACCESS_2_SHADER_STORAGE_READ_BIT, + [PANVK_SUBQUEUE_COMPUTE] = VK_ACCESS_2_UNIFORM_READ_BIT | + VK_ACCESS_2_TRANSFER_READ_BIT | + VK_ACCESS_2_SHADER_SAMPLED_READ_BIT | + VK_ACCESS_2_SHADER_STORAGE_READ_BIT, }; /* Note on the cache organization: