From 06d493dde22f112754365e35f263cb384ccb7b3b Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 30 May 2022 14:41:08 +0800 Subject: [PATCH] radeonsi: implement two esgs ring nir intrinsic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit nir_intrinsic_load_ring_esgs_amd nir_intrinsic_load_ring_es2gs_offset_amd Will be used by esgs lowering. Reviewed-by: Marek Olšák Reviewed-by: Timur Kristóf Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 1 + src/gallium/drivers/radeonsi/si_shader_llvm.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 0d1a5167762..e2fc6ba990c 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3619,6 +3619,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_ring_tess_offchip_amd: case nir_intrinsic_load_ring_tess_offchip_offset_amd: case nir_intrinsic_load_ring_esgs_amd: + case nir_intrinsic_load_ring_es2gs_offset_amd: case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_tcs_num_patches_amd: case nir_intrinsic_load_hs_out_patch_data_offset_amd: diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index 09b663a192e..12585b18ff2 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -790,6 +790,12 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin case nir_intrinsic_load_tess_rel_patch_id_amd: return si_get_rel_patch_id(ctx); + case nir_intrinsic_load_ring_esgs_amd: + return ctx->esgs_ring; + + case nir_intrinsic_load_ring_es2gs_offset_amd: + return ac_get_arg(&ctx->ac, ctx->args.es2gs_offset); + default: return NULL; }