From 06978e0c0ce45e9c1a40dd472a67689046470a82 Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Mon, 3 Mar 2025 09:58:54 +0100 Subject: [PATCH] ir3/cse: add support for mov a0.x/a1.x Signed-off-by: Job Noorman Part-of: --- src/freedreno/ir3/ir3_cse.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/freedreno/ir3/ir3_cse.c b/src/freedreno/ir3/ir3_cse.c index bd03863506a..ac5199c547f 100644 --- a/src/freedreno/ir3/ir3_cse.c +++ b/src/freedreno/ir3/ir3_cse.c @@ -24,6 +24,7 @@ hash_instr(const void *data) hash = HASH(hash, instr->opc); hash = HASH(hash, instr->dsts[0]->flags); + hash = HASH(hash, instr->dsts[0]->num); foreach_src (src, (struct ir3_instruction *)instr) { if (src->flags & IR3_REG_CONST) { if (src->flags & IR3_REG_RELATIV) @@ -63,6 +64,9 @@ instrs_equal(const struct ir3_instruction *i1, const struct ir3_instruction *i2) if (i1->dsts[0]->flags != i2->dsts[0]->flags) return false; + if (i1->dsts[0]->num != i2->dsts[0]->num) + return false; + for (unsigned i = 0; i < i1->srcs_count; i++) { const struct ir3_register *i1_reg = i1->srcs[i], *i2_reg = i2->srcs[i]; @@ -106,6 +110,9 @@ instr_can_cse(const struct ir3_instruction *instr) if (instr->opc != OPC_META_COLLECT && instr->opc != OPC_MOV) return false; + if (reg_num(instr->dsts[0]) == REG_A0) + return true; + if (!is_dest_gpr(instr->dsts[0]) || (instr->dsts[0]->flags & IR3_REG_ARRAY)) return false;