From 05e6d945ad1822509441bd7d59787255ba9e85d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 21 Feb 2023 00:30:21 +0100 Subject: [PATCH] radv: Emulate VGT_ESGS_ITEMSIZE in shaders on GFX9+. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_nir_lower_abi.c | 10 +++++++--- src/amd/vulkan/radv_pipeline.c | 12 +++++++----- src/amd/vulkan/si_cmd_buffer.c | 4 ++++ 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index f3aa5c5354e..51774f50317 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -281,10 +281,14 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) replacement = nir_imm_int(b, io_num * 16); break; } - case nir_intrinsic_load_esgs_vertex_stride_amd: - /* TODO: pass the value of VGT_ESGS_RING_ITEMSIZE here and set the register to 1. */ - replacement = nir_imm_int(b, 1); + case nir_intrinsic_load_esgs_vertex_stride_amd: { + /* Emulate VGT_ESGS_RING_ITEMSIZE on GFX9+ to reduce context register writes. */ + assert(s->gfx_level >= GFX9); + const unsigned stride = s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize + : s->info->gs_ring_info.vgt_esgs_ring_itemsize; + replacement = nir_imm_int(b, stride); break; + } case nir_intrinsic_load_hs_out_patch_data_offset_amd: { unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out; unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ? diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index d7bc40750d0..98215b4b845 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3977,9 +3977,6 @@ radv_pipeline_emit_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs S_028A84_PRIMITIVEID_EN(es_enable_prim_id) | S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id)); - radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, - ngg_state->vgt_esgs_ring_itemsize); - /* NGG specific registers. */ struct radv_shader *gs = pipeline->base.shaders[MESA_SHADER_GEOMETRY]; uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1; @@ -4180,8 +4177,13 @@ radv_pipeline_emit_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0)); - radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, - gs_state->vgt_esgs_ring_itemsize); + if (pdevice->rad_info.gfx_level <= GFX8) { + /* GFX6-8: ESGS offchip ring buffer is allocated according to VGT_ESGS_RING_ITEMSIZE. + * GFX9+: Only used to set the GS input VGPRs, emulated in shaders. + */ + radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, + gs_state->vgt_esgs_ring_itemsize); + } va = radv_shader_get_va(gs); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index e399282f1ff..943feea5d88 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -214,6 +214,10 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) if (physical_device->rad_info.gfx_level <= GFX8) si_set_raster_config(physical_device, cs); + /* Emulated in shader code on GFX9+. */ + if (physical_device->rad_info.gfx_level >= GFX9) + radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 1); + radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); if (!has_clear_state) radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));