diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c index 7d9fd31c637..a5347085191 100644 --- a/src/amd/common/ac_cmdbuf.c +++ b/src/amd/common/ac_cmdbuf.c @@ -1062,10 +1062,10 @@ ac_emit_cp_copy_data(struct ac_cmdbuf *cs, uint32_t src_sel, uint32_t dst_sel, } void -ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs) +ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs, bool predicate) { ac_cmdbuf_begin(cs); - ac_cmdbuf_emit(PKT3(PKT3_PFP_SYNC_ME, 0, 0)); + ac_cmdbuf_emit(PKT3(PKT3_PFP_SYNC_ME, 0, predicate)); ac_cmdbuf_emit(0); ac_cmdbuf_end(); } diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h index ec722534ecb..9ac058a9d76 100644 --- a/src/amd/common/ac_cmdbuf.h +++ b/src/amd/common/ac_cmdbuf.h @@ -132,7 +132,7 @@ ac_emit_cp_copy_data(struct ac_cmdbuf *cs, uint32_t src_sel, uint32_t dst_sel, enum ac_cp_copy_data_flags flags); void -ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs); +ac_emit_cp_pfp_sync_me(struct ac_cmdbuf *cs, bool predicate); void ac_emit_cp_set_predication(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 64ec5e37a28..5e65715c094 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -5076,7 +5076,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct rad ac_emit_cp_copy_data(cs->b, COPY_DATA_SRC_MEM, COPY_DATA_REG, va, reg >> 2, (reg_count == 2 ? AC_CP_COPY_DATA_COUNT_SEL : 0)); - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); } } @@ -14670,7 +14670,7 @@ radv_begin_conditional_rendering(struct radv_cmd_buffer *cmd_buffer, uint64_t va ac_emit_cp_copy_data(cs->b, COPY_DATA_SRC_MEM, COPY_DATA_DST_MEM, va, emulated_va, AC_CP_COPY_DATA_WR_CONFIRM); - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); pred_op = PREDICATION_OP_BOOL64; @@ -15103,7 +15103,7 @@ radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_d /* Emitting a COPY_DATA packet should be enough because RADV doesn't support preemption * (shadow memory) but for unknown reasons, it can lead to GPU hangs on GFX10+. */ - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); radeon_begin(cs); radeon_emit(PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, 0)); diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index cbe4b430743..3a42a00f494 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -316,7 +316,7 @@ gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_lev RADV_CMD_FLAG_CS_PARTIAL_FLUSH))) && !is_mec) { /* We need to ensure that PFP waits as well. */ - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); *sqtt_flush_bits |= RGP_FLUSH_PFP_SYNC_ME; } @@ -488,7 +488,7 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e if ((cp_coher_cntl || (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2))) && !is_mec) { - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); *sqtt_flush_bits |= RGP_FLUSH_PFP_SYNC_ME; } diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index 070295b72f2..44b3de85653 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -605,7 +605,7 @@ radv_pc_wait_idle(struct radv_cmd_buffer *cmd_buffer) radeon_emit(0); /* GCR_CNTL */ radeon_end(); - ac_emit_cp_pfp_sync_me(cs->b); + ac_emit_cp_pfp_sync_me(cs->b, false); } static void diff --git a/src/gallium/drivers/radeonsi/si_cp_utils.c b/src/gallium/drivers/radeonsi/si_cp_utils.c index a4dfefb1a07..9599c13ecd7 100644 --- a/src/gallium/drivers/radeonsi/si_cp_utils.c +++ b/src/gallium/drivers/radeonsi/si_cp_utils.c @@ -101,5 +101,5 @@ void si_cp_acquire_mem(struct si_context *sctx, struct radeon_cmdbuf *cs, unsign void si_cp_pfp_sync_me(struct radeon_cmdbuf *cs) { - ac_emit_cp_pfp_sync_me(&cs->current); + ac_emit_cp_pfp_sync_me(&cs->current, false); }