diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c index 53ec9001f40..af15298b9e0 100644 --- a/src/amd/common/ac_nir.c +++ b/src/amd/common/ac_nir.c @@ -5,6 +5,7 @@ */ #include "ac_nir.h" +#include "ac_nir_helpers.h" #include "sid.h" #include "nir_builder.h" #include "nir_xfb_info.h" @@ -1410,7 +1411,7 @@ split_pack_half(nir_builder *b, nir_instr *instr, void *param) b->cursor = nir_before_instr(instr); - /* Split pack_half into two f2f16 to create v_fma_mix{lo,hi}_f16 + /* Split pack_half into two f2f16 to create v_fma_mix{lo,hi}_f16 * in the backend. */ nir_def *lo = nir_f2f16(b, nir_ssa_for_alu_src(b, alu, 0)); diff --git a/src/amd/common/ac_nir.h b/src/amd/common/ac_nir.h index 762a85f0bdb..258a31068e9 100644 --- a/src/amd/common/ac_nir.h +++ b/src/amd/common/ac_nir.h @@ -12,7 +12,6 @@ #include "ac_shader_args.h" #include "ac_shader_util.h" #include "nir.h" -#include "nir_builder.h" #ifdef __cplusplus extern "C" { @@ -70,47 +69,6 @@ bool ac_nir_lower_intrinsics_to_args(nir_shader *shader, const enum amd_gfx_leve const enum ac_hw_stage hw_stage, const struct ac_shader_args *ac_args); -void -ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value, - unsigned component, unsigned writemask); - -void -ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row); - -void -ac_nir_export_position(nir_builder *b, - enum amd_gfx_level gfx_level, - uint32_t clip_cull_mask, - bool no_param_export, - bool force_vrs, - bool done, - uint64_t outputs_written, - nir_def *(*outputs)[4], - nir_def *row); - -void -ac_nir_export_parameters(nir_builder *b, - const uint8_t *param_offsets, - uint64_t outputs_written, - uint16_t outputs_written_16bit, - nir_def *(*outputs)[4], - nir_def *(*outputs_16bit_lo)[4], - nir_def *(*outputs_16bit_hi)[4]); - -nir_def * -ac_nir_calc_io_offset(nir_builder *b, - nir_intrinsic_instr *intrin, - nir_def *base_stride, - unsigned component_stride, - ac_nir_map_io_driver_location map_io); - -nir_def * -ac_nir_calc_io_offset_mapped(nir_builder *b, - nir_intrinsic_instr *intrin, - nir_def *base_stride, - unsigned component_stride, - unsigned mapped_location); - bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed, int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS], uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]); @@ -218,14 +176,6 @@ ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader, unsigned task_payload_entry_bytes, unsigned task_num_entries); -nir_def * -ac_nir_cull_primitive(nir_builder *b, - nir_def *initially_accepted, - nir_def *pos[3][4], - unsigned num_vertices, - ac_nir_cull_accepted accept_func, - void *state); - bool ac_nir_lower_global_access(nir_shader *shader); @@ -361,35 +311,6 @@ ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4); bool ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level); -#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \ - do { \ - if ((store_val)->bit_size >= 32) { \ - const unsigned store_write_mask = (write_mask); \ - const unsigned store_const_offset = (const_offset); \ - func((b), (store_val), __VA_ARGS__); \ - } else { \ - u_foreach_bit(c, (write_mask)) { \ - const unsigned store_write_mask = 1; \ - const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \ - nir_def *store_component = nir_channel(b, (store_val), c); \ - func((b), store_component, __VA_ARGS__); \ - } \ - } \ - } while (0) - -#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \ - do { \ - const unsigned load_bit_size = MAX2(32, (bit_size)); \ - (load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \ - if ((bit_size) < load_bit_size) { \ - if ((hi_16bit)) { \ - (load) = nir_unpack_32_2x16_split_y(b, load); \ - } else { \ - (load) = nir_unpack_32_2x16_split_x(b, load); \ - } \ - } \ - } while (0) - #ifdef __cplusplus } #endif diff --git a/src/amd/common/ac_nir_cull.c b/src/amd/common/ac_nir_cull.c index 8a6bdf514f7..fc2b6a54fc8 100644 --- a/src/amd/common/ac_nir_cull.c +++ b/src/amd/common/ac_nir_cull.c @@ -6,6 +6,7 @@ */ #include "ac_nir.h" +#include "ac_nir_helpers.h" #include "nir_builder.h" /* This code is adapted from ac_llvm_cull.c, hence the copyright to AMD. */ diff --git a/src/amd/common/ac_nir_helpers.h b/src/amd/common/ac_nir_helpers.h new file mode 100644 index 00000000000..6364f25ad1c --- /dev/null +++ b/src/amd/common/ac_nir_helpers.h @@ -0,0 +1,112 @@ +/* + * Copyright © 2024 Valve Corporation + * + * SPDX-License-Identifier: MIT + */ + + +#ifndef AC_NIR_HELPERS_H +#define AC_NIR_HELPERS_H + +#include "ac_hw_stage.h" +#include "ac_shader_args.h" +#include "ac_shader_util.h" +#include "nir.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define AC_NIR_STORE_IO(b, store_val, const_offset, write_mask, hi_16bit, func, ...) \ + do { \ + if ((store_val)->bit_size >= 32) { \ + const unsigned store_write_mask = (write_mask); \ + const unsigned store_const_offset = (const_offset); \ + func((b), (store_val), __VA_ARGS__); \ + } else { \ + u_foreach_bit(c, (write_mask)) { \ + const unsigned store_write_mask = 1; \ + const unsigned store_const_offset = (const_offset) + c * 4 + ((hi_16bit) ? 2 : 0); \ + nir_def *store_component = nir_channel(b, (store_val), c); \ + func((b), store_component, __VA_ARGS__); \ + } \ + } \ + } while (0) + +#define AC_NIR_LOAD_IO(load, b, num_components, bit_size, hi_16bit, func, ...) \ + do { \ + const unsigned load_bit_size = MAX2(32, (bit_size)); \ + (load) = func((b), (num_components), load_bit_size, __VA_ARGS__); \ + if ((bit_size) < load_bit_size) { \ + if ((hi_16bit)) { \ + (load) = nir_unpack_32_2x16_split_y(b, load); \ + } else { \ + (load) = nir_unpack_32_2x16_split_x(b, load); \ + } \ + } \ + } while (0) + +/* Maps I/O semantics to the actual location used by the lowering pass. */ +typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic); + +/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */ +struct nir_builder; +typedef struct nir_builder nir_builder; + +/* Executed by ac_nir_cull when the current primitive is accepted. */ +typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state); + +void +ac_nir_store_var_components(nir_builder *b, nir_variable *var, nir_def *value, + unsigned component, unsigned writemask); + +void +ac_nir_export_primitive(nir_builder *b, nir_def *prim, nir_def *row); + +void +ac_nir_export_position(nir_builder *b, + enum amd_gfx_level gfx_level, + uint32_t clip_cull_mask, + bool no_param_export, + bool force_vrs, + bool done, + uint64_t outputs_written, + nir_def *(*outputs)[4], + nir_def *row); + +void +ac_nir_export_parameters(nir_builder *b, + const uint8_t *param_offsets, + uint64_t outputs_written, + uint16_t outputs_written_16bit, + nir_def *(*outputs)[4], + nir_def *(*outputs_16bit_lo)[4], + nir_def *(*outputs_16bit_hi)[4]); + +nir_def * +ac_nir_calc_io_offset(nir_builder *b, + nir_intrinsic_instr *intrin, + nir_def *base_stride, + unsigned component_stride, + ac_nir_map_io_driver_location map_io); + +nir_def * +ac_nir_calc_io_offset_mapped(nir_builder *b, + nir_intrinsic_instr *intrin, + nir_def *base_stride, + unsigned component_stride, + unsigned mapped_location); + +nir_def * +ac_nir_cull_primitive(nir_builder *b, + nir_def *initially_accepted, + nir_def *pos[3][4], + unsigned num_vertices, + ac_nir_cull_accepted accept_func, + void *state); + +#ifdef __cplusplus +} +#endif + +#endif /* AC_NIR_HELPERS_H */ diff --git a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c index 534adb23945..7c16abadee0 100644 --- a/src/amd/common/ac_nir_lower_esgs_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_esgs_io_to_mem.c @@ -5,6 +5,7 @@ */ #include "ac_nir.h" +#include "ac_nir_helpers.h" #include "nir_builder.h" /* diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index 47f34b062b4..d48733ae224 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -5,6 +5,7 @@ */ #include "ac_nir.h" +#include "ac_nir_helpers.h" #include "amdgfxregs.h" #include "nir_builder.h" #include "nir_xfb_info.h" diff --git a/src/amd/common/ac_nir_lower_subdword_loads.c b/src/amd/common/ac_nir_lower_subdword_loads.c index 1c74c5bab4b..c73076f6c7d 100644 --- a/src/amd/common/ac_nir_lower_subdword_loads.c +++ b/src/amd/common/ac_nir_lower_subdword_loads.c @@ -23,6 +23,7 @@ #include "util/u_math.h" #include "ac_nir.h" +#include "nir_builder.h" static bool lower_subdword_loads(nir_builder *b, nir_instr *instr, void *data) diff --git a/src/amd/common/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/ac_nir_lower_tess_io_to_mem.c index e5975e40514..cf696235909 100644 --- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c @@ -5,6 +5,7 @@ */ #include "ac_nir.h" +#include "ac_nir_helpers.h" #include "nir_builder.h" /* diff --git a/src/amd/common/meson.build b/src/amd/common/meson.build index 04154180264..e4e8d4b23d4 100644 --- a/src/amd/common/meson.build +++ b/src/amd/common/meson.build @@ -92,6 +92,7 @@ amd_common_files = files( 'ac_msgpack.h', 'ac_nir.c', 'ac_nir.h', + 'ac_nir_helpers.h', 'ac_nir_opt_outputs.c', 'ac_nir_cull.c', 'ac_nir_lower_esgs_io_to_mem.c',