From 0367dc1e4263c55ba4dbdb49e98a0b29de1af987 Mon Sep 17 00:00:00 2001 From: Simon Perretta Date: Tue, 4 Feb 2025 16:46:40 +0000 Subject: [PATCH] pco, pvr: sample mask out support Signed-off-by: Simon Perretta Acked-by: Erik Faye-Lund Part-of: --- src/compiler/nir/nir_intrinsics.py | 3 +++ src/imagination/pco/pco_map.py | 31 +++++++++++++++++++++++++++++ src/imagination/pco/pco_nir_pvfio.c | 15 ++++++++++++++ src/imagination/pco/pco_ops.py | 2 ++ src/imagination/pco/pco_trans_nir.c | 13 ++++++++++++ 5 files changed, 64 insertions(+) diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index ff7c55c19bc..55203d482b6 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -2728,3 +2728,6 @@ intrinsic("mutex_pco", indices=[MUTEX_ID_PCO, MUTEX_OP_PCO]) # depthf_pco(depth value) # Perform an ISP depth feedback operation. intrinsic("depthf_pco", src_comp=[1], bit_sizes=[32]) + +# Loads the valid mask. +intrinsic("load_savmsk_vm_pco", src_comp=[], dest_comp=1, indices=[], flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) diff --git a/src/imagination/pco/pco_map.py b/src/imagination/pco/pco_map.py index baad11284f1..29b2beafd2d 100644 --- a/src/imagination/pco/pco_map.py +++ b/src/imagination/pco/pco_map.py @@ -342,6 +342,14 @@ enum_map(OM_MTX_OP.t, F_LR, [ ('lock', 'lock'), ]) +enum_map(OM_SAVMSK_MODE.t, F_MSK_MODE, [ + ('vm', 'vm'), + ('icm', 'icm'), + ('icmoc', 'icmoc'), + ('icmi', 'icmi'), + ('caxy', 'caxy'), +]) + class OpRef(object): def __init__(self, ref_type, index, mods): self.type = ref_type @@ -1439,6 +1447,11 @@ encode_map(O_DEPTHF, op_ref_maps=[('backend', [], ['drc', 'w0'])] ) +encode_map(O_SAVMSK, + encodings=[(I_SAVMSK, [('msk_mode', OM_SAVMSK_MODE)])], + op_ref_maps=[('backend', [['w0', '_'], ['w1', '_']], [])] +) + encode_map(O_BBYP0BM, encodings=[ (I_PHASE0_SRC, [ @@ -2867,6 +2880,24 @@ group_map(O_DEPTHF, ] ) +group_map(O_SAVMSK, + hdr=(I_IGRP_HDR_MAIN, [ + ('oporg', 'be'), + ('olchk', OM_OLCHK), + ('w1p', ('!pco_ref_is_null', DEST(1))), + ('w0p', ('!pco_ref_is_null', DEST(0))), + ('cc', OM_EXEC_CND), + ('end', OM_END), + ('atom', OM_ATOM), + ('rpt', 1) + ]), + enc_ops=[('backend', O_SAVMSK)], + dests=[ + ('w[0]', ('backend', DEST(0)), 'w0'), + ('w[1]', ('backend', DEST(1)), 'w1') + ] +) + group_map(O_MOVI32, hdr=(I_IGRP_HDR_BITWISE, [ ('opcnt', 'p0'), diff --git a/src/imagination/pco/pco_nir_pvfio.c b/src/imagination/pco/pco_nir_pvfio.c index b02242eb58d..6e45b9aeda5 100644 --- a/src/imagination/pco/pco_nir_pvfio.c +++ b/src/imagination/pco/pco_nir_pvfio.c @@ -913,6 +913,21 @@ static nir_def *lower_pfo(nir_builder *b, nir_instr *instr, void *cb_data) return NIR_LOWER_INSTR_PROGRESS_REPLACE; } + if (sem.location == FRAG_RESULT_SAMPLE_MASK) { + nir_def *smp_msk = + nir_ishl(b, nir_imm_int(b, 1), nir_load_sample_id(b)); + + smp_msk = nir_iand(b, smp_msk, intr->src[0].ssa); + smp_msk = nir_iand(b, smp_msk, nir_load_savmsk_vm_pco(b)); + nir_def *cond = nir_ieq_imm(b, smp_msk, 0); + + state->has_discards = true; + nir_def *val = nir_load_reg(b, state->discard_cond_reg); + val = nir_ior(b, val, cond); + nir_store_reg(b, val, state->discard_cond_reg); + return NIR_LOWER_INSTR_PROGRESS_REPLACE; + } + UNREACHABLE(""); } diff --git a/src/imagination/pco/pco_ops.py b/src/imagination/pco/pco_ops.py index f3e46a93c2d..38a4dd83569 100644 --- a/src/imagination/pco/pco_ops.py +++ b/src/imagination/pco/pco_ops.py @@ -393,6 +393,8 @@ O_ALPHATST = hw_op('alphatst', OM_ALU_RPT1, 1, 4) O_ALPHAF = hw_op('alphaf', OM_ALU_RPT1, 1, 4) O_DEPTHF = hw_op('depthf', OM_ALU_RPT1, 0, 2) +O_SAVMSK = hw_op('savmsk', OM_ALU_RPT1 + [OM_SAVMSK_MODE], 2) + ## Bitwise. O_MOVI32 = hw_op('movi32', OM_ALU, 1, 1) diff --git a/src/imagination/pco/pco_trans_nir.c b/src/imagination/pco/pco_trans_nir.c index 481102d3850..58112e0de24 100644 --- a/src/imagination/pco/pco_trans_nir.c +++ b/src/imagination/pco/pco_trans_nir.c @@ -1356,6 +1356,19 @@ static pco_instr *trans_intr(trans_ctx *tctx, nir_intrinsic_instr *intr) pco_ref_hwreg(PCO_SR_INST_NUM, PCO_REG_CLASS_SPEC)); break; + case nir_intrinsic_load_sample_id: + instr = pco_mov(&tctx->b, + dest, + pco_ref_hwreg(PCO_SR_SAMP_NUM, PCO_REG_CLASS_SPEC)); + break; + + case nir_intrinsic_load_savmsk_vm_pco: + instr = pco_savmsk(&tctx->b, + dest, + pco_ref_null(), + .savmsk_mode = PCO_SAVMSK_MODE_VM); + break; + case nir_intrinsic_decl_reg: case nir_intrinsic_load_reg: case nir_intrinsic_store_reg: