From 0324d4bcf53a9f20f0f852995c4f76ebc9f6c3e2 Mon Sep 17 00:00:00 2001 From: Michael Cheng Date: Sun, 11 Aug 2024 15:16:58 -0700 Subject: [PATCH] anv: move trace logic to batch_emit_pipe_control_write Move trace logic from cmd_buffer_apply_pipe_flushes down to genX(batch_emit_pipe_control_write). Signed-off-by: Michael Cheng Part-of: --- src/intel/vulkan/anv_batch_chain.c | 1 + src/intel/vulkan/anv_private.h | 14 ++++---- src/intel/vulkan/genX_cmd_buffer.c | 51 ++++++++++++++++-------------- 3 files changed, 36 insertions(+), 30 deletions(-) diff --git a/src/intel/vulkan/anv_batch_chain.c b/src/intel/vulkan/anv_batch_chain.c index 3c082db3496..83685dab532 100644 --- a/src/intel/vulkan/anv_batch_chain.c +++ b/src/intel/vulkan/anv_batch_chain.c @@ -879,6 +879,7 @@ anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->batch.extend_cb = anv_cmd_buffer_chain_batch; cmd_buffer->batch.engine_class = cmd_buffer->queue_family->engine_class; + cmd_buffer->batch.trace = &cmd_buffer->trace; anv_batch_bo_start(batch_bo, &cmd_buffer->batch, GFX9_MI_BATCH_BUFFER_START_length * 4); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 644358648f9..516f32c87ea 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2346,6 +2346,11 @@ struct anv_batch { * Number of 3DPRIMITIVE's emitted for WA 16014538804 */ uint8_t num_3d_primitives_emitted; + + struct u_trace * trace; + const char * pc_reasons[4]; + uint32_t pc_reasons_count; + }; void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords); @@ -3926,8 +3931,6 @@ struct anv_cmd_state { struct anv_cmd_ray_tracing_state rt; enum anv_pipe_bits pending_pipe_bits; - const char * pc_reasons[4]; - uint32_t pc_reasons_count; /** * Whether the last programmed STATE_BASE_ADDRESS references @@ -6153,11 +6156,8 @@ anv_add_pending_pipe_bits(struct anv_cmd_buffer* cmd_buffer, anv_dump_pipe_bits(bits, stdout); fprintf(stdout, "reason: %s\n", reason); } - /* store reason, if space available*/ - if (cmd_buffer->state.pc_reasons_count < - ARRAY_SIZE(cmd_buffer->state.pc_reasons)) { - cmd_buffer->state.pc_reasons[ - cmd_buffer->state.pc_reasons_count++] = reason; + if (cmd_buffer->batch.pc_reasons_count < ARRAY_SIZE(cmd_buffer->batch.pc_reasons)) { + cmd_buffer->batch.pc_reasons[cmd_buffer->batch.pc_reasons_count++] = reason; } } diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 57ddc0b76ac..8b8b1263025 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1824,14 +1824,6 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) return; } - const bool trace_flush = - (bits & (ANV_PIPE_FLUSH_BITS | - ANV_PIPE_STALL_BITS | - ANV_PIPE_INVALIDATE_BITS | - ANV_PIPE_END_OF_PIPE_SYNC_BIT)) != 0; - if (trace_flush) - trace_intel_begin_stall(&cmd_buffer->trace); - if (GFX_VER == 9 && (bits & ANV_PIPE_CS_STALL_BIT) && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) { @@ -1844,7 +1836,6 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) sizeof(cmd_buffer->state.gfx.ib_dirty_range)); } - enum anv_pipe_bits emitted_bits = 0; cmd_buffer->state.pending_pipe_bits = genX(emit_apply_pipe_flushes)(&cmd_buffer->batch, @@ -1866,20 +1857,6 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) } #endif - if (trace_flush) { - trace_intel_end_stall(&cmd_buffer->trace, - bits & ~cmd_buffer->state.pending_pipe_bits, - anv_pipe_flush_bit_to_ds_stall_flag, - cmd_buffer->state.pc_reasons[0], - cmd_buffer->state.pc_reasons[1], - cmd_buffer->state.pc_reasons[2], - cmd_buffer->state.pc_reasons[3]); - cmd_buffer->state.pc_reasons[0] = NULL; - cmd_buffer->state.pc_reasons[1] = NULL; - cmd_buffer->state.pc_reasons[2] = NULL; - cmd_buffer->state.pc_reasons[3] = NULL; - cmd_buffer->state.pc_reasons_count = 0; - } } static inline struct anv_state @@ -2428,6 +2405,20 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, (batch->engine_class == INTEL_ENGINE_CLASS_VIDEO)) unreachable("Trying to emit unsupported PIPE_CONTROL command."); + const bool trace_flush = + (bits & (ANV_PIPE_FLUSH_BITS | + ANV_PIPE_STALL_BITS | + ANV_PIPE_INVALIDATE_BITS | + ANV_PIPE_END_OF_PIPE_SYNC_BIT)) != 0; + if (trace_flush && batch->trace != NULL) { + // Store pipe control reasons if there is enough space + if (batch->pc_reasons_count < ARRAY_SIZE(batch->pc_reasons)) { + batch->pc_reasons[batch->pc_reasons_count++] = reason; + } + trace_intel_begin_stall(batch->trace); + } + + /* XXX - insert all workarounds and GFX specific things below. */ /* Wa_14014966230: For COMPUTE Workload - Any PIPE_CONTROL command with @@ -2564,6 +2555,20 @@ genX(batch_emit_pipe_control_write)(struct anv_batch *batch, anv_debug_dump_pc(pipe, reason); } + + if (trace_flush && batch->trace != NULL) { + trace_intel_end_stall(batch->trace, bits, + anv_pipe_flush_bit_to_ds_stall_flag, + batch->pc_reasons[0], + batch->pc_reasons[1], + batch->pc_reasons[2], + batch->pc_reasons[3]); + batch->pc_reasons[0] = NULL; + batch->pc_reasons[1] = NULL; + batch->pc_reasons[2] = NULL; + batch->pc_reasons[3] = NULL; + batch->pc_reasons_count = 0; + } } /* Set preemption on/off. */