From 015e3e34a71baf08f9cf7d34f806ff4b4659d524 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 30 Dec 2024 10:34:37 +0100 Subject: [PATCH] radv/meta: convert the HW resolve GFX pipelines to vk_meta Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/meta/radv_meta.c | 5 - src/amd/vulkan/meta/radv_meta.h | 3 - src/amd/vulkan/meta/radv_meta_resolve.c | 252 ++++++++++-------------- src/amd/vulkan/radv_device.h | 5 - 4 files changed, 99 insertions(+), 166 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta.c b/src/amd/vulkan/meta/radv_meta.c index a6fe0bf34fb..3af49990a4d 100644 --- a/src/amd/vulkan/meta/radv_meta.c +++ b/src/amd/vulkan/meta/radv_meta.c @@ -459,10 +459,6 @@ radv_device_init_meta(struct radv_device *device) if (result != VK_SUCCESS) return result; - result = radv_device_init_meta_resolve_state(device, on_demand); - if (result != VK_SUCCESS) - return result; - result = radv_device_init_meta_blit_state(device, on_demand); if (result != VK_SUCCESS) return result; @@ -518,7 +514,6 @@ radv_device_finish_meta(struct radv_device *device) radv_device_finish_meta_astc_decode_state(device); radv_device_finish_accel_struct_build_state(device); radv_device_finish_meta_clear_state(device); - radv_device_finish_meta_resolve_state(device); radv_device_finish_meta_blit_state(device); radv_device_finish_meta_blit2d_state(device); radv_device_finish_meta_fast_clear_flush_state(device); diff --git a/src/amd/vulkan/meta/radv_meta.h b/src/amd/vulkan/meta/radv_meta.h index 59eedd3f16e..f9215a15236 100644 --- a/src/amd/vulkan/meta/radv_meta.h +++ b/src/amd/vulkan/meta/radv_meta.h @@ -108,9 +108,6 @@ void radv_device_finish_meta(struct radv_device *device); VkResult radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand); void radv_device_finish_meta_clear_state(struct radv_device *device); -VkResult radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand); -void radv_device_finish_meta_resolve_state(struct radv_device *device); - VkResult radv_device_init_meta_fast_clear_flush_state(struct radv_device *device, bool on_demand); void radv_device_finish_meta_fast_clear_flush_state(struct radv_device *device); diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c index 31a419fc3b7..eb81e375117 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve.c +++ b/src/amd/vulkan/meta/radv_meta_resolve.c @@ -29,179 +29,124 @@ build_nir_fs(struct radv_device *dev) } static VkResult -create_pipeline(struct radv_device *device, VkFormat format, VkPipeline *pipeline) +get_pipeline(struct radv_device *device, unsigned fs_key, VkPipeline *pipeline_out, VkPipelineLayout *layout_out) { + const VkFormat format = radv_fs_key_format_exemplars[fs_key]; + char key_data[64]; VkResult result; - VkDevice device_h = radv_device_to_handle(device); - if (!device->meta_state.resolve.p_layout) { - result = radv_meta_create_pipeline_layout(device, NULL, 0, NULL, &device->meta_state.resolve.p_layout); - if (result != VK_SUCCESS) - return result; - } + snprintf(key_data, sizeof(key_data), "radv-resolve-hw-%d", fs_key); + + result = vk_meta_get_pipeline_layout(&device->vk, &device->meta_state.device, NULL, NULL, key_data, + strlen(key_data), layout_out); + if (result != VK_SUCCESS) + return result; nir_shader *vs_module = radv_meta_build_nir_vs_generate_vertices(device); nir_shader *fs_module = build_nir_fs(device); - VkFormat color_formats[2] = {format, format}; - const VkPipelineRenderingCreateInfo rendering_create_info = { - .sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO, - .colorAttachmentCount = 2, - .pColorAttachmentFormats = color_formats, - }; - const VkGraphicsPipelineCreateInfoRADV radv_info = { .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO_RADV, - .pNext = &rendering_create_info, .custom_blend_mode = V_028808_CB_RESOLVE, }; - result = radv_CreateGraphicsPipelines( - device_h, device->meta_state.cache, 1, - &(VkGraphicsPipelineCreateInfo){ - .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO, - .pNext = &radv_info, - .stageCount = 2, - .pStages = - (VkPipelineShaderStageCreateInfo[]){ - { - .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, - .stage = VK_SHADER_STAGE_VERTEX_BIT, - .module = vk_shader_module_handle_from_nir(vs_module), - .pName = "main", - }, - { - .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, - .stage = VK_SHADER_STAGE_FRAGMENT_BIT, - .module = vk_shader_module_handle_from_nir(fs_module), - .pName = "main", - }, + const VkGraphicsPipelineCreateInfo pipeline_create_info = { + .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO, + .pNext = &radv_info, + .stageCount = 2, + .pStages = + (VkPipelineShaderStageCreateInfo[]){ + { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_VERTEX_BIT, + .module = vk_shader_module_handle_from_nir(vs_module), + .pName = "main", }, - .pVertexInputState = - &(VkPipelineVertexInputStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO, - .vertexBindingDescriptionCount = 0, - .vertexAttributeDescriptionCount = 0, + { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_FRAGMENT_BIT, + .module = vk_shader_module_handle_from_nir(fs_module), + .pName = "main", }, - .pInputAssemblyState = - &(VkPipelineInputAssemblyStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, - .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, - .primitiveRestartEnable = false, - }, - .pViewportState = - &(VkPipelineViewportStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO, - .viewportCount = 1, - .scissorCount = 1, - }, - .pRasterizationState = - &(VkPipelineRasterizationStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO, - .depthClampEnable = false, - .rasterizerDiscardEnable = false, - .polygonMode = VK_POLYGON_MODE_FILL, - .cullMode = VK_CULL_MODE_NONE, - .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE, - }, - .pMultisampleState = - &(VkPipelineMultisampleStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO, - .rasterizationSamples = 1, - .sampleShadingEnable = false, - .pSampleMask = NULL, - .alphaToCoverageEnable = false, - .alphaToOneEnable = false, - }, - .pColorBlendState = - &(VkPipelineColorBlendStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO, - .logicOpEnable = false, - .attachmentCount = 2, - .pAttachments = - (VkPipelineColorBlendAttachmentState[]){ - { - .colorWriteMask = VK_COLOR_COMPONENT_R_BIT | VK_COLOR_COMPONENT_G_BIT | - VK_COLOR_COMPONENT_B_BIT | VK_COLOR_COMPONENT_A_BIT, - }, - { - .colorWriteMask = 0, - - }}, - }, - .pDynamicState = - &(VkPipelineDynamicStateCreateInfo){ - .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO, - .dynamicStateCount = 2, - .pDynamicStates = - (VkDynamicState[]){ - VK_DYNAMIC_STATE_VIEWPORT, - VK_DYNAMIC_STATE_SCISSOR, + }, + .pVertexInputState = + &(VkPipelineVertexInputStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO, + .vertexBindingDescriptionCount = 0, + .vertexAttributeDescriptionCount = 0, + }, + .pInputAssemblyState = + &(VkPipelineInputAssemblyStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, + .topology = VK_PRIMITIVE_TOPOLOGY_META_RECT_LIST_MESA, + .primitiveRestartEnable = false, + }, + .pViewportState = + &(VkPipelineViewportStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO, + .viewportCount = 1, + .scissorCount = 1, + }, + .pRasterizationState = + &(VkPipelineRasterizationStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO, + .depthClampEnable = false, + .rasterizerDiscardEnable = false, + .polygonMode = VK_POLYGON_MODE_FILL, + .cullMode = VK_CULL_MODE_NONE, + .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE, + }, + .pMultisampleState = + &(VkPipelineMultisampleStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO, + .rasterizationSamples = 1, + .sampleShadingEnable = false, + .pSampleMask = NULL, + .alphaToCoverageEnable = false, + .alphaToOneEnable = false, + }, + .pColorBlendState = + &(VkPipelineColorBlendStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO, + .logicOpEnable = false, + .attachmentCount = 2, + .pAttachments = + (VkPipelineColorBlendAttachmentState[]){ + { + .colorWriteMask = VK_COLOR_COMPONENT_R_BIT | VK_COLOR_COMPONENT_G_BIT | VK_COLOR_COMPONENT_B_BIT | + VK_COLOR_COMPONENT_A_BIT, }, - }, - .layout = device->meta_state.resolve.p_layout, - .renderPass = VK_NULL_HANDLE, - .subpass = 0, - }, - &device->meta_state.alloc, pipeline); + { + .colorWriteMask = 0, + + }}, + }, + .pDynamicState = + &(VkPipelineDynamicStateCreateInfo){ + .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO, + .dynamicStateCount = 2, + .pDynamicStates = + (VkDynamicState[]){ + VK_DYNAMIC_STATE_VIEWPORT, + VK_DYNAMIC_STATE_SCISSOR, + }, + }, + .layout = *layout_out, + }; + + struct vk_meta_rendering_info render = { + .color_attachment_count = 2, + .color_attachment_formats = {format, format}, + }; + + result = vk_meta_create_graphics_pipeline(&device->vk, &device->meta_state.device, &pipeline_create_info, &render, + key_data, strlen(key_data), pipeline_out); ralloc_free(vs_module); ralloc_free(fs_module); return result; } -static VkResult -get_pipeline(struct radv_device *device, unsigned fs_key, VkPipeline *pipeline_out) -{ - struct radv_meta_state *state = &device->meta_state; - VkResult result = VK_SUCCESS; - - mtx_lock(&state->mtx); - if (!state->resolve.pipeline[fs_key]) { - result = create_pipeline(device, radv_fs_key_format_exemplars[fs_key], &state->resolve.pipeline[fs_key]); - if (result != VK_SUCCESS) - goto fail; - } - - *pipeline_out = state->resolve.pipeline[fs_key]; - -fail: - mtx_unlock(&state->mtx); - return result; -} - -void -radv_device_finish_meta_resolve_state(struct radv_device *device) -{ - struct radv_meta_state *state = &device->meta_state; - - for (uint32_t j = 0; j < NUM_META_FS_KEYS; j++) { - radv_DestroyPipeline(radv_device_to_handle(device), state->resolve.pipeline[j], &state->alloc); - } - radv_DestroyPipelineLayout(radv_device_to_handle(device), state->resolve.p_layout, &state->alloc); -} - -VkResult -radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand) -{ - if (on_demand) - return VK_SUCCESS; - - VkResult res = VK_SUCCESS; - struct radv_meta_state *state = &device->meta_state; - - for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) { - VkFormat format = radv_fs_key_format_exemplars[i]; - unsigned fs_key = radv_format_meta_fs_key(device, format); - - res = create_pipeline(device, format, &state->resolve.pipeline[fs_key]); - if (res != VK_SUCCESS) - return res; - } - - return res; -} - static void emit_resolve(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image, const struct radv_image *dst_image, VkFormat vk_format) @@ -209,10 +154,11 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_im struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer); unsigned fs_key = radv_format_meta_fs_key(device, vk_format); + VkPipelineLayout layout; VkPipeline pipeline; VkResult result; - result = get_pipeline(device, fs_key, &pipeline); + result = get_pipeline(device, fs_key, &pipeline, &layout); if (result != VK_SUCCESS) { vk_command_buffer_set_error(&cmd_buffer->vk, result); return; diff --git a/src/amd/vulkan/radv_device.h b/src/amd/vulkan/radv_device.h index cac3932a676..f919cd7ce92 100644 --- a/src/amd/vulkan/radv_device.h +++ b/src/amd/vulkan/radv_device.h @@ -141,11 +141,6 @@ struct radv_meta_state { VkPipeline stencil_only_pipeline[5]; } blit2d[MAX_SAMPLES_LOG2]; - struct { - VkPipelineLayout p_layout; - VkPipeline pipeline[NUM_META_FS_KEYS]; - } resolve; - struct { VkDescriptorSetLayout ds_layout; VkPipelineLayout p_layout;