From 0120e7b9d9e9523e9d5689d1d394f35117c3e0dc Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Wed, 10 Aug 2022 13:20:32 +0300
Subject: [PATCH] freedreno: PC_SO_STREAM_CNTL_STREAM_ENABLE has per-stream
 enable bits

PC_SO_STREAM_CNTL.STREAM_ENABLE mirrors VPC_SO_STREAM_CNTL.STREAM_ENABLE

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>
---
 src/freedreno/registers/adreno/a6xx.xml          | 2 +-
 src/gallium/drivers/freedreno/a6xx/fd6_program.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index d199a623503..060a9541d46 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2592,7 +2592,7 @@ to upconvert to 32b float internally?
 
 	<!-- New in a6xx gen3+ -->
 	<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL">
-		<bitfield name="STREAM_ENABLE" pos="15" type="boolean"/>
+		<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
 	</reg32>
 
 	<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 5ddc48152f5..c0125ef1c03 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -281,7 +281,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
        * tess + xfb fails some tests if we don't emit this.
        */
       OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
-      OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE);
+      OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(0x1));
    }
 
    state->streamout_stateobj = ring;