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radv,aco: move radv_ps_epilog_key to the graphics pipeline key

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To avoid redundant structs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20199>
This commit is contained in:
Samuel Pitoiset
2022-12-08 13:55:34 +01:00
committed by Marge Bot
parent 67c9497435
commit 011a0b97b2
7 changed files with 51 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/compiler/aco_instruction_selection.cpp
+7 -6
View File
@@ -11484,7 +11484,7 @@ create_fs_exports(isel_context* ctx)
* require MRT0 to be written. Just copy MRT1 into MRT0. Skipping MRT1 exports seems to be
* fine.
*/
if (ctx->options->key.ps.mrt0_is_dual_src && !ctx->outputs.mask[FRAG_RESULT_DATA0] &&
if (ctx->options->key.ps.epilog.mrt0_is_dual_src && !ctx->outputs.mask[FRAG_RESULT_DATA0] &&
ctx->outputs.mask[FRAG_RESULT_DATA1]) {
u_foreach_bit (j, ctx->outputs.mask[FRAG_RESULT_DATA1]) {
ctx->outputs.temps[FRAG_RESULT_DATA0 * 4u + j] =
@@ -11506,10 +11506,11 @@ create_fs_exports(isel_context* ctx)
out.slot = compacted_mrt_index;
out.write_mask = ctx->outputs.mask[i];
out.col_format = (ctx->options->key.ps.spi_shader_col_format >> (4 * idx)) & 0xf;
out.is_int8 = (ctx->options->key.ps.color_is_int8 >> idx) & 1;
out.is_int10 = (ctx->options->key.ps.color_is_int10 >> idx) & 1;
out.enable_mrt_output_nan_fixup = (ctx->options->key.ps.enable_mrt_output_nan_fixup >> idx) & 1;
out.col_format = (ctx->options->key.ps.epilog.spi_shader_col_format >> (4 * idx)) & 0xf;
out.is_int8 = (ctx->options->key.ps.epilog.color_is_int8 >> idx) & 1;
out.is_int10 = (ctx->options->key.ps.epilog.color_is_int10 >> idx) & 1;
out.enable_mrt_output_nan_fixup =
(ctx->options->key.ps.epilog.enable_mrt_output_nan_fixup >> idx) & 1;
for (unsigned c = 0; c < 4; ++c) {
if (out.write_mask & (1 << c)) {
@@ -11526,7 +11527,7 @@ create_fs_exports(isel_context* ctx)
}
if (exported) {
if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.mrt0_is_dual_src) {
if (ctx->options->gfx_level >= GFX11 && ctx->options->key.ps.epilog.mrt0_is_dual_src) {
struct aco_export_mrt* mrt0 = mrts[0].enabled_channels ? &mrts[0] : NULL;
struct aco_export_mrt* mrt1 = mrts[1].enabled_channels ? &mrts[1] : NULL;
create_fs_dual_src_export_gfx11(ctx, mrt0, mrt1);
src/amd/compiler/aco_shader_info.h
+12 -16
View File
@@ -60,17 +60,6 @@ struct aco_vs_prolog_key {
gl_shader_stage next_stage;
};
struct aco_ps_epilog_key {
uint32_t spi_shader_col_format;
/* Bitmasks, each bit represents one of the 8 MRTs. */
uint8_t color_is_int8;
uint8_t color_is_int10;
uint8_t enable_mrt_output_nan_fixup;
bool mrt0_is_dual_src;
};
struct aco_vp_output_info {
uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
uint8_t clip_dist_mask;
@@ -138,6 +127,17 @@ enum aco_compiler_debug_level {
ACO_COMPILER_DEBUG_LEVEL_ERROR,
};
struct aco_ps_epilog_key {
uint32_t spi_shader_col_format;
/* Bitmasks, each bit represents one of the 8 MRTs. */
uint8_t color_is_int8;
uint8_t color_is_int10;
uint8_t enable_mrt_output_nan_fixup;
bool mrt0_is_dual_src;
};
struct aco_stage_input {
uint32_t optimisations_disabled : 1;
uint32_t image_2d_view_of_3d : 1;
@@ -156,14 +156,10 @@ struct aco_stage_input {
} tcs;
struct {
uint32_t spi_shader_col_format;
uint8_t color_is_int8;
uint8_t color_is_int10;
uint8_t enable_mrt_output_nan_fixup;
struct aco_ps_epilog_key epilog;
/* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
bool alpha_to_coverage_via_mrtz;
bool mrt0_is_dual_src;
} ps;
};