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radeonsi: use native shader info when init streamout args

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We are going to init shader args earlier, there is no such
pipe_stream_output_info when that time.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18010>
This commit is contained in:
Qiang Yu
2022-08-05 16:24:05 +08:00
committed by Marge Bot
parent c445c29263
commit 003cbddfee
1 changed files with 6 additions and 7 deletions
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src/gallium/drivers/radeonsi/si_shader.c
+6 -7
View File
@@ -196,8 +196,7 @@ static void si_dump_streamout(struct pipe_stream_output_info *so)
} }
} }
static void declare_streamout_params(struct si_shader_context *ctx, static void declare_streamout_params(struct si_shader_context *ctx)
struct pipe_stream_output_info *so)
{ {
if (ctx->screen->use_ngg_streamout) { if (ctx->screen->use_ngg_streamout) {
if (ctx->stage == MESA_SHADER_TESS_EVAL) if (ctx->stage == MESA_SHADER_TESS_EVAL)
@@ -206,7 +205,7 @@ static void declare_streamout_params(struct si_shader_context *ctx,
} }
/* Streamout SGPRs. */ /* Streamout SGPRs. */
if (so->num_outputs) { if (si_shader_uses_streamout(ctx->shader)) {
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_config); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_config);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_write_index); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_write_index);
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) { } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
@@ -215,7 +214,7 @@ static void declare_streamout_params(struct si_shader_context *ctx,
/* A streamout buffer offset is loaded if the stride is non-zero. */ /* A streamout buffer offset is loaded if the stride is non-zero. */
for (int i = 0; i < 4; i++) { for (int i = 0; i < 4; i++) {
if (!so->stride[i]) if (!ctx->shader->selector->info.base.xfb_stride[i])
continue; continue;
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_offset[i]); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.streamout_offset[i]);
@@ -431,7 +430,7 @@ void si_init_shader_args(struct si_shader_context *ctx)
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->vs_state_bits);
if (ctx->shader->is_gs_copy_shader) { if (ctx->shader->is_gs_copy_shader) {
declare_streamout_params(ctx, &ctx->so); declare_streamout_params(ctx);
/* VGPRs */ /* VGPRs */
declare_vs_input_vgprs(ctx, &num_prolog_vgprs); declare_vs_input_vgprs(ctx, &num_prolog_vgprs);
break; break;
@@ -447,7 +446,7 @@ void si_init_shader_args(struct si_shader_context *ctx)
} else if (shader->key.ge.as_ls) { } else if (shader->key.ge.as_ls) {
/* no extra parameters */ /* no extra parameters */
} else { } else {
declare_streamout_params(ctx, &ctx->so); declare_streamout_params(ctx);
} }
/* VGPRs */ /* VGPRs */
@@ -636,7 +635,7 @@ void si_init_shader_args(struct si_shader_context *ctx)
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, NULL);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.es2gs_offset); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.es2gs_offset);
} else { } else {
declare_streamout_params(ctx, &ctx->so); declare_streamout_params(ctx);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset); ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset);
} }